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<p>In the semiconductor industry, plasma etching has become a key process for fabricating precise and reliable patterns with high aspect ratios capacitors (HARC), allowing for complex device architectures. During continuous etching operations, the focus ring gradually erodes as a crucial component for maintaining plasma uniformity, particularly at the wafer edge. This degradation results in plasma instability and sheath distortion at the edge, leading to non-uniform etch profiles, tilting, and reduced productivity. This study investigates the effect of applying a separated DC edge bias to achieve more uniform plasma conditions and highly directional ion incidence by controlling the plasma sheath potential. The implementation of localized DC voltages at the edge enhanced etching uniformity and mitigated tilting issues, thereby showing the formation of well-defined and vertical trench. However, high DC voltages exceeding 280&#xa0;V generated harmful current flow from the edge to the wafer center, which triggered plasma instability and impaired precise sheath control. This electrical interference and etching non-uniformity were alleviated by modifying the impedance ratio of the focus ring to the wafer chuck. As a result, the proposed approach is expected to improve etching efficiency and overall yield in fabrication of next-generation memory devices.</p>

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Enhancing uniformity in HARC etching via edge bias voltage and structural impedance variations in a rectangular voltage waveform

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年1月20日

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  • Chanho Park,
  • Jinill Cho,
  • Junghwan Um,
  • Taesung Kim

摘要

In the semiconductor industry, plasma etching has become a key process for fabricating precise and reliable patterns with high aspect ratios capacitors (HARC), allowing for complex device architectures. During continuous etching operations, the focus ring gradually erodes as a crucial component for maintaining plasma uniformity, particularly at the wafer edge. This degradation results in plasma instability and sheath distortion at the edge, leading to non-uniform etch profiles, tilting, and reduced productivity. This study investigates the effect of applying a separated DC edge bias to achieve more uniform plasma conditions and highly directional ion incidence by controlling the plasma sheath potential. The implementation of localized DC voltages at the edge enhanced etching uniformity and mitigated tilting issues, thereby showing the formation of well-defined and vertical trench. However, high DC voltages exceeding 280 V generated harmful current flow from the edge to the wafer center, which triggered plasma instability and impaired precise sheath control. This electrical interference and etching non-uniformity were alleviated by modifying the impedance ratio of the focus ring to the wafer chuck. As a result, the proposed approach is expected to improve etching efficiency and overall yield in fabrication of next-generation memory devices.