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<p>As a nanoscale computing paradigm, quantum-dot cellular automata (QCA) technology demonstrates significant advantages over conventional CMOS implementations, including improved device density, minimized power dissipation, and increased operational speed. As fundamental building blocks in QCA architectures, time-to-digital converters (TDCs) enable the operation of all-digital delay-locked loops, systems paramount to contemporary timing solutions. These digital loops particularly excel in applications requiring (1) multi-phase clock synthesis and (2) sub-clock-cycle temporal resolution. This work introduces an optimized QCA-based TDC with 228 cells (30% reduction) and 0.2668&#xa0;μm<sup>2</sup> area. The design achieve delay of 1 QCA clock cycle and 40% lower complexity than conventional approaches. Our architecture enables precise timing for digital PLLs/DLLs in nanoelectronics. The compact cell arrangement overcomes CMOS scaling limits through QCA’s nanowatt power and terahertz speeds. These advancements position QCA-TDCs as prime candidates for next-gen terahertz computing systems. Simulation outcomes validate the effectiveness of the developed architecture, marking a significant step forward in the practical realization of QCA-based timing circuits.</p>

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Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年5月5日

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  • Shahram Modanlou,
  • Mohammad Gholami

摘要

As a nanoscale computing paradigm, quantum-dot cellular automata (QCA) technology demonstrates significant advantages over conventional CMOS implementations, including improved device density, minimized power dissipation, and increased operational speed. As fundamental building blocks in QCA architectures, time-to-digital converters (TDCs) enable the operation of all-digital delay-locked loops, systems paramount to contemporary timing solutions. These digital loops particularly excel in applications requiring (1) multi-phase clock synthesis and (2) sub-clock-cycle temporal resolution. This work introduces an optimized QCA-based TDC with 228 cells (30% reduction) and 0.2668 μm2 area. The design achieve delay of 1 QCA clock cycle and 40% lower complexity than conventional approaches. Our architecture enables precise timing for digital PLLs/DLLs in nanoelectronics. The compact cell arrangement overcomes CMOS scaling limits through QCA’s nanowatt power and terahertz speeds. These advancements position QCA-TDCs as prime candidates for next-gen terahertz computing systems. Simulation outcomes validate the effectiveness of the developed architecture, marking a significant step forward in the practical realization of QCA-based timing circuits.