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<p>We present a quantitative analysis of synaptic characteristics dependent on a read voltage (V<sub>read</sub>) of a sub-threshold operating Hf-ZnO synaptic thin-film transistor (Syn-TFT). As an higher case with V<sub>read</sub> = 2.3&#xa0;V near the threshold voltage (V<sub>T</sub>), the output current is depressed with applying positive programming-pulses, which is due to a positive V<sub>T</sub> shift associated with the electron trapping into the gate insulator. For a lower case with V<sub>read</sub> = 0.6&#xa0;V around the flat-band voltage (V<sub>FB</sub>), negative programming-pulses are applied to get de-trapping electrons from the gate insulator, resulting in a facilitation of the output current associated with a negative V<sub>T</sub> shift. During the weight-update process, it is observed that the programming-speed for a lower V<sub>read</sub> is faster compared to a higher V<sub>read</sub> due to the steeper sub-threshold slope. After the programming processes, the retention characteristics is monitored with applying constant V<sub>read</sub>, showing that the effective retention time for a higher V<sub>read</sub> is much longer than that for a lower V<sub>read</sub>. This is because a higher positive bias stress can lead to a positive V<sub>T</sub> shift, suppressing the recovery of trapped electrons. Here, it is found that the bias stress can be intentionally used to improve the retention time.</p>

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A read voltage dependent synaptic characteristics of sub-threshold thin film transistors with a hf doped ZnO active layer

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  • 发表日期：

    2025年4月17日

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  • Jeongseok Pi,
  • Danyoung Cha,
  • Sungsik Lee

摘要

We present a quantitative analysis of synaptic characteristics dependent on a read voltage (Vread) of a sub-threshold operating Hf-ZnO synaptic thin-film transistor (Syn-TFT). As an higher case with Vread = 2.3 V near the threshold voltage (VT), the output current is depressed with applying positive programming-pulses, which is due to a positive VT shift associated with the electron trapping into the gate insulator. For a lower case with Vread = 0.6 V around the flat-band voltage (VFB), negative programming-pulses are applied to get de-trapping electrons from the gate insulator, resulting in a facilitation of the output current associated with a negative VT shift. During the weight-update process, it is observed that the programming-speed for a lower Vread is faster compared to a higher Vread due to the steeper sub-threshold slope. After the programming processes, the retention characteristics is monitored with applying constant Vread, showing that the effective retention time for a higher Vread is much longer than that for a lower Vread. This is because a higher positive bias stress can lead to a positive VT shift, suppressing the recovery of trapped electrons. Here, it is found that the bias stress can be intentionally used to improve the retention time.