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<p>A switched-capacitor (SC)-based, single-stage, seven-level (7&#xa0;L) inverter with a common ground is proposed to address the need for efficient and reliable power conversion in modern applications. Existing multilevel inverter (MLI) topologies often suffer from high voltage stress, increased THD, and complex control requirements. This study aims to design a compact inverter with improved performance metrics, including efficiency, total harmonic distortion (THD), and voltage stress. The proposed inverter employs a single DC source, 8 switches, 2 diodes, and 3 capacitors, achieving a threefold voltage boost without requiring additional control for self-balancing capacitor voltages. Nearest level pulse width modulation (PWM) is used to generate switching pulses, while reliability analysis ensures a robust system under short-circuit and open-circuit faults. Efficiency and power losses are evaluated using PLECS thermal modeling, and SC selection criteria are discussed to enhance performance. Results indicate that the proposed inverter achieves an efficiency of 97.4% for a 600&#xa0;W load, reduced leakage current, improvements in THD, minimized conduction loss, and high-power density. To verify the suggested inverter performance, a valid thorough comparison of other recent CGSC-7&#xa0;L topologies and MLIs with the suggested topology has been provided. Experimental validations under various loading and modulation conditions confirm the simulation outcomes, showcasing the inverter’s robust and dynamic performance.</p>

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Design and analysis of a single source seven level common ground SC based multilevel inverter topology with high reliability

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年7月27日

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  • Md Tahmid Hussain,
  • Adil Sarwar,
  • Md Reyaz Hussan,
  • Mohd Tariq,
  • Shafiq Ahmad,
  • Farhad Ilahi Bakhsh,
  • Mohammad Zaid,
  • Adamali Shah Noor Mohamed,
  • Baseem Khan

摘要

A switched-capacitor (SC)-based, single-stage, seven-level (7 L) inverter with a common ground is proposed to address the need for efficient and reliable power conversion in modern applications. Existing multilevel inverter (MLI) topologies often suffer from high voltage stress, increased THD, and complex control requirements. This study aims to design a compact inverter with improved performance metrics, including efficiency, total harmonic distortion (THD), and voltage stress. The proposed inverter employs a single DC source, 8 switches, 2 diodes, and 3 capacitors, achieving a threefold voltage boost without requiring additional control for self-balancing capacitor voltages. Nearest level pulse width modulation (PWM) is used to generate switching pulses, while reliability analysis ensures a robust system under short-circuit and open-circuit faults. Efficiency and power losses are evaluated using PLECS thermal modeling, and SC selection criteria are discussed to enhance performance. Results indicate that the proposed inverter achieves an efficiency of 97.4% for a 600 W load, reduced leakage current, improvements in THD, minimized conduction loss, and high-power density. To verify the suggested inverter performance, a valid thorough comparison of other recent CGSC-7 L topologies and MLIs with the suggested topology has been provided. Experimental validations under various loading and modulation conditions confirm the simulation outcomes, showcasing the inverter’s robust and dynamic performance.