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<p>In this work, a novel deep trench CSTBT (DT-CSTBT) features emitter trench and the P-layer is proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, demonstrates an excellent clamping effect potential. The proposed DT-CSTBT suppresses the saturation current and improves the heat dissipation, resulting in a 23.5% expansion of the short-circuit safe operating area (SCSOA). It ensures the better reliability of the gate due to the high electric field away from the gate. Furthermore, the tradeoff relationship between on-state voltage (<i>V</i><sub>ON</sub>) and turn-off loss (<i>E</i><sub>off</sub>) of the new structure is also improved by 23.2% compared with the conventional CSTBT.</p>

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A novel self-biased pMOS clamped deep trench CSTBT with enhanced tradeoff and short-circuit capability

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年1月8日

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  • Jianbin Guo,
  • Zhehong Qian,
  • Xinru Chen,
  • Hang Xu,
  • Yafen Yang,
  • David Wei Zhang

摘要

In this work, a novel deep trench CSTBT (DT-CSTBT) features emitter trench and the P-layer is proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, demonstrates an excellent clamping effect potential. The proposed DT-CSTBT suppresses the saturation current and improves the heat dissipation, resulting in a 23.5% expansion of the short-circuit safe operating area (SCSOA). It ensures the better reliability of the gate due to the high electric field away from the gate. Furthermore, the tradeoff relationship between on-state voltage (VON) and turn-off loss (Eoff) of the new structure is also improved by 23.2% compared with the conventional CSTBT.