Scholarlink

<p>Ge<sub>1−x</sub>Sn<sub>x</sub> and Si<sub>1−x−y</sub>Ge<sub>y</sub>Sn<sub>x</sub> alloys are promising materials for future nanoelectronic applications owing to their high carrier mobilities and CMOS compatibility. However, ternary Si<sub>1−x−y</sub>Ge<sub>y</sub>Sn<sub>x</sub> transistors have only theoretically been discussed, and there are only a few reports on lateral n-type Ge<sub>1−x</sub>Sn<sub>x</sub> transistors to benchmark their material performance. The low equilibrium solid solubility of Sn in Si<sub>1−x</sub>Ge<sub>x</sub> (less than 1 at%) requires device fabrication processes at temperatures below the growth temperature of Si<sub>1−x−y</sub>Ge<sub>y</sub>Sn<sub>x</sub> (x &gt; equilibrium solubility) or at non-equilibrium conditions. Therefore, Si-based processes need to be adjusted according to the materials requirements. A relatively easy-to-fabricate device concept are junctionless field effect transistors, which operate as a gated resistor. In this work, we use Ge<sub>0.94</sub>Sn<sub>0.06</sub> and Si<sub>0.14</sub>Ge<sub>0.80</sub>Sn<sub>0.06</sub> grown on silicon-on-insulator substrates to fabricate and characterize lateral n-type Ge<sub>1−x</sub>Sn<sub>x</sub> and Si<sub>y</sub>Ge<sub>1−x−y</sub>Sn<sub>x</sub> junctionless field effect transistors. The transistors were structurally characterized by top-view scanning electron microscopy and cross-sectional transmission electron microscopy. Electrical characterizations by transfer characteristics show the first working n-type Ge<sub>1−x</sub>Sn<sub>x</sub> and Si<sub>1−x−y</sub>Ge<sub>y</sub>Sn<sub>x</sub> hetero-nanowire transistors, achieving on/off-current ratios of up to eight orders of magnitude.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Fabrication and characterization of n-type Ge1−xSnx- and Si1–x–yGeySnx-on-SOI junctionless transistors

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年12月26日

查看全文
  • Oliver Steuer,
  • Sayantan Ghosh,
  • Daniel Schwarz,
  • Michael Oehme,
  • Sebastian Lehmann,
  • René Hübner,
  • Ciarán Fowley,
  • Artur Erbe,
  • Shengqiang Zhou,
  • Manfred Helm,
  • Gianaurelio Cuniberti,
  • Slawomir Prucnal,
  • Yordan M. Georgiev

摘要

Ge1−xSnx and Si1−x−yGeySnx alloys are promising materials for future nanoelectronic applications owing to their high carrier mobilities and CMOS compatibility. However, ternary Si1−x−yGeySnx transistors have only theoretically been discussed, and there are only a few reports on lateral n-type Ge1−xSnx transistors to benchmark their material performance. The low equilibrium solid solubility of Sn in Si1−xGex (less than 1 at%) requires device fabrication processes at temperatures below the growth temperature of Si1−x−yGeySnx (x > equilibrium solubility) or at non-equilibrium conditions. Therefore, Si-based processes need to be adjusted according to the materials requirements. A relatively easy-to-fabricate device concept are junctionless field effect transistors, which operate as a gated resistor. In this work, we use Ge0.94Sn0.06 and Si0.14Ge0.80Sn0.06 grown on silicon-on-insulator substrates to fabricate and characterize lateral n-type Ge1−xSnx and SiyGe1−x−ySnx junctionless field effect transistors. The transistors were structurally characterized by top-view scanning electron microscopy and cross-sectional transmission electron microscopy. Electrical characterizations by transfer characteristics show the first working n-type Ge1−xSnx and Si1−x−yGeySnx hetero-nanowire transistors, achieving on/off-current ratios of up to eight orders of magnitude.