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<p>A successive approximation register analog-to-digital converter (SAR ADC) is a promising approach used in biomedical applications due to its energy-efficiency architecture with less complex hardware implementation. The core building blocks of SAR ADC are sample-and-hold switch (S/H), comparator, logic control register, and digital-to-analog converter (DAC). To enhance the overall performance, a high-isolation CMOS bootstrap S/H switch has been used. The SFDR of proposed ADC has increased by up to 2.2 dB. Also, we propose a double-tail single-ended dynamic latch comparator with extra pair PMOS transistors that save power by up to 7.5% as compared to the traditional double-tail dynamic comparator. Moreover, after adding these pair of transistors into conventional double tail dynamic comparator without any calibration cost, the SNDR has increased by more than 2 dB and 0.3bit improvement of ENOB. Furthermore, a synchronous modified SAR logic control register based on low-power D flip-flops (FFs) is proposed. A metal-isolator-metal capacitor (MIM) with a modified capacitance reduction configuration is used to improve the active area of the capacitive DAC (CDAC) compared to the conventional CDAC with 36.7% saving power. The proposed ADC has been implemented using a 65-nm TSMC CMOS process, 1.2&#xa0;V supply voltage with a sampling rate of 1 MS/s. An active area of 0.00585 mm<sup>2</sup> with a total post-result power consumption of 5.75 µW has been accomplished for the proposed fully integrated ADC.</p>

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A 1.2-V 7.76-ENOB 1-MS/s single-ended SAR ADC in 65-nm CMOS for biomedical applications

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年11月5日

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  • Kawther I. Arafa,
  • Dina M. Ellaithy,
  • Heba Shawkey,
  • Mohamed Abouelatta,
  • Abdelhalim Zekry

摘要

A successive approximation register analog-to-digital converter (SAR ADC) is a promising approach used in biomedical applications due to its energy-efficiency architecture with less complex hardware implementation. The core building blocks of SAR ADC are sample-and-hold switch (S/H), comparator, logic control register, and digital-to-analog converter (DAC). To enhance the overall performance, a high-isolation CMOS bootstrap S/H switch has been used. The SFDR of proposed ADC has increased by up to 2.2 dB. Also, we propose a double-tail single-ended dynamic latch comparator with extra pair PMOS transistors that save power by up to 7.5% as compared to the traditional double-tail dynamic comparator. Moreover, after adding these pair of transistors into conventional double tail dynamic comparator without any calibration cost, the SNDR has increased by more than 2 dB and 0.3bit improvement of ENOB. Furthermore, a synchronous modified SAR logic control register based on low-power D flip-flops (FFs) is proposed. A metal-isolator-metal capacitor (MIM) with a modified capacitance reduction configuration is used to improve the active area of the capacitive DAC (CDAC) compared to the conventional CDAC with 36.7% saving power. The proposed ADC has been implemented using a 65-nm TSMC CMOS process, 1.2 V supply voltage with a sampling rate of 1 MS/s. An active area of 0.00585 mm2 with a total post-result power consumption of 5.75 µW has been accomplished for the proposed fully integrated ADC.