<p>Employing the Booth algorithm to generate partial products and utilizing the Wallace tree method for compressing these products significantly enhance the speed of multipliers. Adopting quaternary logic can effectively reduce the number of operand and multiplier bits by half compared to binary logic. Therefore, if the Booth algorithm is implemented in quaternary logic in such a way that the transistor count per digit of partial products remains approximately the same as in binary logic, it is expected that the delay and area of the multiplier will decrease due to the reduction in the number of partial product rows and the halving of the partial products per row. In this study, the multiplier is designed under the assumption that both inputs and outputs operate in a quaternary system. A novel method is proposed for determining the sign bit and representing signed numbers in quaternary logic, ensuring that the processed data in quaternary logic can be seamlessly converted to binary logic. Additionally, a direct encoding technique is introduced to represent quaternary multiple bits in the conventional 16th-order Booth algorithm used in binary logic. Furthermore, a parallel doubler is designed in quaternary logic, and an efficient method is presented for implementing a quaternary Booth decoder with minimal hardware, making it comparable to its binary counterpart. The proposed quaternary compressors are employed to compress partial products, and a technique is introduced to prevent sign-bit expansion in quaternary logic, thereby reducing hardware consumption during the compression stage. To evaluate the proposed approach in designing a 16th-order Booth multiplier in quaternary logic, all proposed units were first simulated using the CNTFET transistor model provided by Stanford University in HSPICE software. Based on the results, the maximum static power consumption and the delay of the proposed Booth multiplier were estimated.</p>