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<p>One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100&#xa0;nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlO<sub>x</sub>/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (<InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41598_2025_8787_Article_IEq1.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="39" /> </InlineMediaObject> <EquationSource Format="TEX">\(\:{CV}_{A}\)</EquationSource> </InlineEquation>) improvement down to 1.1% for the critical dimensions from 130 × 170 nm<sup>2</sup> to 130 × 670 nm<sup>2</sup> over 70 × 70 mm<sup>2</sup> (49 cm<sup>2</sup>) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving <InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="41598_2025_8787_Article_IEq2.gif" Format="GIF" Height="19" Rendition="HTML" Resolution="72" Type="Linedraw" Width="47" /> </InlineMediaObject> <EquationSource Format="TEX">\(\:{CV}_{{R}_{N}}\)</EquationSource> </InlineEquation> down to 6.0/5.2/4.1% for 0.025 µm<sup>2</sup> JJ area and 4.0/3.4/2.3% for 0.090 µm<sup>2</sup> JJ area for 49/25/16 cm<sup>2</sup> wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.</p>

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Wafer-scale uniformity improvement of Dolan-bridge Josephson junction by shadow evaporation bias correction

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年8月1日

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  • Daria A. Moskaleva,
  • Nikita D. Korshakov,
  • Dmitry O. Moskalev,
  • Anastasiya A. Soloveva,
  • Alexey R. Matanin,
  • Elizaveta I. Malevannaya,
  • Nikita S. Smirnov,
  • Maksim I. Teleganov,
  • Yuri V. Panfilov,
  • Ilya A. Rodionov

摘要

One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient ( \(\:{CV}_{A}\) ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving \(\:{CV}_{{R}_{N}}\) down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.