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<p>This article presents a technique in nanoscale field effect diode structure to overcome the challenges in conventional field effect diode structures. By reducing the impurity, the amount of additional minority carriers injected from the source and drain areas into the channel and the possibility of band-to-band tunneling between the reservoirs is reduced. But with the decrease of impurity, the ON current also decreases. Using the properties of germanium material in the field effect diode has led to an increase in the ON current, a decrease in gate delay, and an increase in the speed of this device compared to conventional silicon-based structures. In addition, due to the small bandgap of germanium compared to silicon, this device can be used in low-power applications. By comparing the results obtained in the proposed structure with conventional structures, the ON/OFF current ratio is 500 times better, as well as the gate delay and EDP have been reduced from 114 to 0.26&#xa0;ps and 5.023 × 10<sup>–26</sup> to 1.87 × 10<sup>–28</sup> j.s, respectively.</p>

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A technique to reduce the probability of band-to-band tunneling for eliminating injected minority carriers in nano scale field-effect diode

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年7月1日

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  • Arash Rezaei,
  • Ali Aaghar Orouji

摘要

This article presents a technique in nanoscale field effect diode structure to overcome the challenges in conventional field effect diode structures. By reducing the impurity, the amount of additional minority carriers injected from the source and drain areas into the channel and the possibility of band-to-band tunneling between the reservoirs is reduced. But with the decrease of impurity, the ON current also decreases. Using the properties of germanium material in the field effect diode has led to an increase in the ON current, a decrease in gate delay, and an increase in the speed of this device compared to conventional silicon-based structures. In addition, due to the small bandgap of germanium compared to silicon, this device can be used in low-power applications. By comparing the results obtained in the proposed structure with conventional structures, the ON/OFF current ratio is 500 times better, as well as the gate delay and EDP have been reduced from 114 to 0.26 ps and 5.023 × 10–26 to 1.87 × 10–28 j.s, respectively.