<p>A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction<sup><CitationRef AdditionalCitationIDS="CR2" CitationID="CR1">1</CitationRef>–<CitationRef CitationID="CR3">3</CitationRef></sup>. However, with each physical qubit needing multiple control lines, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware<sup><CitationRef AdditionalCitationIDS="CR5" CitationID="CR4">4</CitationRef>–<CitationRef CitationID="CR6">6</CitationRef></sup>. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired up by miniaturized interconnects<sup><CitationRef AdditionalCitationIDS="CR8 CR9" CitationID="CR7">7</CitationRef>–<CitationRef CitationID="CR10">10</CitationRef></sup>. Even so, heat and crosstalk from closely integrated control have the potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise<sup><CitationRef CitationID="CR11">11</CitationRef>,<CitationRef CitationID="CR12">12</CitationRef></sup>. Here we benchmark silicon metal-oxide-semiconductor (MOS)-style electron spin qubits controlled by heterogeneously integrated cryo-complementary metal-oxide-semiconductor (cryo-CMOS) circuits with a power density sufficiently low to enable scale-up. Demonstrating that cryo-CMOS can efficiently perform universal logic operations for spin qubits, we go on to show that milli-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our sub-kelvin CMOS platform, with about 100,000 transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a ‘chiplet-style’ control architecture.</p>

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Spin-qubit control with a milli-kelvin CMOS chip

  • Samuel K. Bartee,
  • Will Gilbert,
  • Kun Zuo,
  • Kushal Das,
  • Tuomo Tanttu,
  • Chih Hwan Yang,
  • Nard Dumoulin Stuyck,
  • Sebastian J. Pauka,
  • Rocky Y. Su,
  • Wee Han Lim,
  • Santiago Serrano,
  • Christopher C. Escott,
  • Fay E. Hudson,
  • Kohei M. Itoh,
  • Arne Laucht,
  • Andrew S. Dzurak,
  • David J. Reilly

摘要

A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction13. However, with each physical qubit needing multiple control lines, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware46. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired up by miniaturized interconnects710. Even so, heat and crosstalk from closely integrated control have the potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise11,12. Here we benchmark silicon metal-oxide-semiconductor (MOS)-style electron spin qubits controlled by heterogeneously integrated cryo-complementary metal-oxide-semiconductor (cryo-CMOS) circuits with a power density sufficiently low to enable scale-up. Demonstrating that cryo-CMOS can efficiently perform universal logic operations for spin qubits, we go on to show that milli-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our sub-kelvin CMOS platform, with about 100,000 transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a ‘chiplet-style’ control architecture.