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<p>Recent advances in quantum error correction in various hardware platforms have demonstrated operation near and beyond the threshold for fault-tolerant quantum computing. However, scaling up to achieve the exponential suppression of logical errors needed for fault tolerance remains challenging. Erasure qubits offer a path towards resource-efficient error correction, which enables the hardware-level detection of dominant error types. Single erasure qubits with dual-rail encoding in superconducting devices have demonstrated high coherence and low single-qubit gate errors with mid-circuit erasure detection. Here we demonstrate the generation of logical multi-qubit entanglement under error-biased protection using pairs of tunable transmons in a superconducting quantum processor. Each dual-rail qubit maintains millisecond-scale coherence times and logical single-qubit gate error rates on the order of 10<sup>−5</sup> by using post-selection to mitigate erasure errors. We then demonstrate a logical <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\sqrt{{\rm{iSWAP}}}\)</EquationSource> <EquationSource Format="MATHML"><math> <msqrt> <mrow> <mi mathvariant="normal">iSWAP</mi> </mrow> </msqrt> </math></EquationSource> </InlineEquation> gate and the generation of a logical Bell state by engineering tunable couplings between the logical qubits. Building on this, we synthesize a logical controlled-NOT gate with a process fidelity of 98.1% at a 13% erasure rate, enabling the creation of a three-logical-qubit Greenberger–Horne–Zeilinger state with 93.9% fidelity.</p>

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Logical multi-qubit entanglement with dual-rail superconducting qubits

  • 期刊论文

  • 发表日期：

    2026年3月6日

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  • Wenhui Huang,
  • Xuandong Sun,
  • Jiawei Zhang,
  • Zechen Guo,
  • Peisheng Huang,
  • Yongqi Liang,
  • Yiting Liu,
  • Daxiong Sun,
  • Zilin Wang,
  • Yuzhe Xiong,
  • Xiaohan Yang,
  • Jiajian Zhang,
  • Libo Zhang,
  • Ji Chu,
  • Weijie Guo,
  • Ji Jiang,
  • Song Liu,
  • Jingjing Niu,
  • Jiawei Qiu,
  • Ziyu Tao,
  • Yuxuan Zhou,
  • Xiayu Linpeng,
  • Youpeng Zhong,
  • Dapeng Yu

摘要

Recent advances in quantum error correction in various hardware platforms have demonstrated operation near and beyond the threshold for fault-tolerant quantum computing. However, scaling up to achieve the exponential suppression of logical errors needed for fault tolerance remains challenging. Erasure qubits offer a path towards resource-efficient error correction, which enables the hardware-level detection of dominant error types. Single erasure qubits with dual-rail encoding in superconducting devices have demonstrated high coherence and low single-qubit gate errors with mid-circuit erasure detection. Here we demonstrate the generation of logical multi-qubit entanglement under error-biased protection using pairs of tunable transmons in a superconducting quantum processor. Each dual-rail qubit maintains millisecond-scale coherence times and logical single-qubit gate error rates on the order of 10−5 by using post-selection to mitigate erasure errors. We then demonstrate a logical \(\sqrt{{\rm{iSWAP}}}\) iSWAP gate and the generation of a logical Bell state by engineering tunable couplings between the logical qubits. Building on this, we synthesize a logical controlled-NOT gate with a process fidelity of 98.1% at a 13% erasure rate, enabling the creation of a three-logical-qubit Greenberger–Horne–Zeilinger state with 93.9% fidelity.