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<p>The foundry industry and academia are confronting the limits of Moore’s Law scaling for logic transistors. Silicon field‑effect transistors (FETs) now rely on gate‑all‑around structures and ultrathin channels, even at the cost of decreased carrier mobility and complex fabrication processes. Two‑dimensional (2D) semiconductors offer a promising alternative because they retain their crystalline quality at atomic thicknesses. Nonetheless, whether they truly exhibit higher performance than silicon remains questionable. Here, by implementing a dual‑gate structure on bilayer MoS<sub>2</sub> FETs, we mitigate the fringing‑field barrier created by the elevated top contact and achieve high carrier densities without increasing fabrication complexity. Simulations and statistical analysis confirm that the dual‑gate compensates the fringe field, enabling a drain current of 1.55 mA µm<sup>−1</sup> even with conventional gold contacts. Quantum‑transport simulation indicates that, with further gate‑length and equivalent‑oxide‑thickness scaling, the on-state current can reach levels comparable to silicon FETs at the 3-nm node, and monolithic 3D integration can extend the applicability of dual‑gate 2D transistors to future logic technologies.</p>

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Gate structuring on n-type bilayer MoS2 field-effect transistors for ultrahigh current density

  • 期刊论文

  • 发表日期：

    2026年1月9日

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  • Junyoung Kwon,
  • Kyoung Yeon Kim,
  • Dongwon Jang,
  • Min Seok Yoo,
  • Alum Jung,
  • Dong-Su Ko,
  • Yoonhoo Ha,
  • Huije Ryu,
  • Woon Ih Choi,
  • Yeonchoo Cho,
  • Changhyun Kim,
  • Eunji Yang,
  • Eun Kyu Lee,
  • Chang-Seok Lee,
  • Sang Won Kim,
  • Uihui Kwon,
  • Dae Sin Kim,
  • Sung Kyu Lim,
  • Kyung-Eun Byun,
  • Minsu Seol,
  • Jeehwan Kim

摘要

The foundry industry and academia are confronting the limits of Moore’s Law scaling for logic transistors. Silicon field‑effect transistors (FETs) now rely on gate‑all‑around structures and ultrathin channels, even at the cost of decreased carrier mobility and complex fabrication processes. Two‑dimensional (2D) semiconductors offer a promising alternative because they retain their crystalline quality at atomic thicknesses. Nonetheless, whether they truly exhibit higher performance than silicon remains questionable. Here, by implementing a dual‑gate structure on bilayer MoS2 FETs, we mitigate the fringing‑field barrier created by the elevated top contact and achieve high carrier densities without increasing fabrication complexity. Simulations and statistical analysis confirm that the dual‑gate compensates the fringe field, enabling a drain current of 1.55 mA µm−1 even with conventional gold contacts. Quantum‑transport simulation indicates that, with further gate‑length and equivalent‑oxide‑thickness scaling, the on-state current can reach levels comparable to silicon FETs at the 3-nm node, and monolithic 3D integration can extend the applicability of dual‑gate 2D transistors to future logic technologies.