<p>Innovations in device architectures and materials promote transistor miniaturization for improved performance, energy efficiency and integration density. At foreseeable ångström nodes, a gate-all-around (GAA) field-effect transistor based on two-dimensional (2D) semiconductors would provide excellent electrostatic gate controllability to achieve ultimate power scaling and performance delivering. However, a major roadblock lies in the scalable integration of 2D GAA heterostructures with atomically smooth and conformal interfaces. Here we report a wafer-scale multi-layer-stacked single-crystalline 2D GAA configuration achieved with low-temperature monolithic three-dimensional integration, in which high-mobility 2D semiconductor Bi<sub>2</sub>O<sub>2</sub>Se was epitaxially integrated by high-<i>κ</i> layered native-oxide dielectric Bi<sub>2</sub>SeO<sub>5</sub> with an atomically smooth interface, enabling a high electron mobility of 280 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup> and a near-ideal subthreshold swing of 62 mV dec<sup>−1</sup>. The scaled 2D GAA field-effect transistor with 30 nm gate length exhibits an ultralow operation voltage of 0.5 V, a high on-state current exceeding 1 mA μm<sup>−1</sup>, an ultralow intrinsic delay of 1.9 ps and an energy-delay product of 1.84 × 10<sup>−27</sup> Js μm<sup>−1</sup>. This work demonstrates a wafer-scale 2D-material-based GAA system with valid performance and power merits, holding promising prospects for beyond-silicon monolithic three-dimensional circuits.</p>

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Low-power 2D gate-all-around logics via epitaxial monolithic 3D integration

  • Junchuan Tang,
  • Jianfeng Jiang,
  • Xiaoyin Gao,
  • Xin Gao,
  • Chenxi Zhang,
  • Mengdi Wang,
  • Chengyuan Xue,
  • Zhongrui Li,
  • Yuling Yin,
  • Congwei Tan,
  • Feng Ding,
  • Chenguang Qiu,
  • Lian-Mao Peng,
  • Hailin Peng

摘要

Innovations in device architectures and materials promote transistor miniaturization for improved performance, energy efficiency and integration density. At foreseeable ångström nodes, a gate-all-around (GAA) field-effect transistor based on two-dimensional (2D) semiconductors would provide excellent electrostatic gate controllability to achieve ultimate power scaling and performance delivering. However, a major roadblock lies in the scalable integration of 2D GAA heterostructures with atomically smooth and conformal interfaces. Here we report a wafer-scale multi-layer-stacked single-crystalline 2D GAA configuration achieved with low-temperature monolithic three-dimensional integration, in which high-mobility 2D semiconductor Bi2O2Se was epitaxially integrated by high-κ layered native-oxide dielectric Bi2SeO5 with an atomically smooth interface, enabling a high electron mobility of 280 cm2 V−1 s−1 and a near-ideal subthreshold swing of 62 mV dec−1. The scaled 2D GAA field-effect transistor with 30 nm gate length exhibits an ultralow operation voltage of 0.5 V, a high on-state current exceeding 1 mA μm−1, an ultralow intrinsic delay of 1.9 ps and an energy-delay product of 1.84 × 10−27 Js μm−1. This work demonstrates a wafer-scale 2D-material-based GAA system with valid performance and power merits, holding promising prospects for beyond-silicon monolithic three-dimensional circuits.