Scholarlink

<p>As conventional silicon scaling approaches fundamental physical limits, two-dimensional semiconductors offer a promising pathway for continued transistor miniaturization. Here we show an ultra-scaled vertical MoS<sub>2</sub> transistor that combines a sub-1&#xa0;nm gate and a 10&#xa0;nm channel length, realized through a dual-self-aligned fabrication strategy. In this architecture, the exposed edge of a monolayer graphene at etched sidewalls serves as an atomically thin gate electrode, while the sidewalls also act as self-aligned masks for defining an ultra-short MoS<sub>2</sub> channel through oblique-angle deposition. This co-scaling strategy yields an on-state current density&#xa0;of 23 μA/μm and on/off current ratio exceeding 10⁶. Systematic device simulations further elucidate the electrostatic control, effective gate length, and tunneling-limited scaling behavior of this vertical architecture. Beyond individual transistors, we demonstrate wafer-scale arrays and their integration into logic circuits (inverters, NAND, NOR gates), underscoring the scalability and integration potential of this platform.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Wafer-scale 2D MoS2 transistors with self-aligned angstrom gate length and nanometer channel length

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年7月11日

查看全文
  • Ziming Wang,
  • Anhan Liu,
  • Hengbin Ding,
  • Fan Wu,
  • Caifang Gao,
  • Yizhe Guo,
  • Ruifang Xue,
  • Peigen Zhang,
  • Yanming Liu,
  • Tao Deng,
  • Tian-Ling Ren,
  • He Tian

摘要

As conventional silicon scaling approaches fundamental physical limits, two-dimensional semiconductors offer a promising pathway for continued transistor miniaturization. Here we show an ultra-scaled vertical MoS2 transistor that combines a sub-1 nm gate and a 10 nm channel length, realized through a dual-self-aligned fabrication strategy. In this architecture, the exposed edge of a monolayer graphene at etched sidewalls serves as an atomically thin gate electrode, while the sidewalls also act as self-aligned masks for defining an ultra-short MoS2 channel through oblique-angle deposition. This co-scaling strategy yields an on-state current density of 23 μA/μm and on/off current ratio exceeding 10⁶. Systematic device simulations further elucidate the electrostatic control, effective gate length, and tunneling-limited scaling behavior of this vertical architecture. Beyond individual transistors, we demonstrate wafer-scale arrays and their integration into logic circuits (inverters, NAND, NOR gates), underscoring the scalability and integration potential of this platform.