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<p>Monolithic three-dimensional integration enables dense vertical stacking of devices with fine-pitch interconnects, offering a promising route toward high-density, energy-efficient logic and memory systems. However, its implementation is constrained by the thermal budget of back-end-of-line processes, which must remain below 400 °C to avoid degrading underlying circuitry. While various low-temperature semiconductors have been explored, current demonstrations remain confined to fixed stacking sequences due to high-temperature growth or transfer requirements. Here, we demonstrate a M3D complementary field-effect transistor architecture using low-temperature-deposited n-type In<sub>2</sub>O<sub>3</sub> and p-type Te semiconductors. This platform resolves existing thermal constraints, demonstrating the design freedom to reverse n- and p-type sequences. This capability enables the integration of CMOS inverters, multilayer logic stacks, and a fully functional 3D SRAM storage cell, all fabricated below 300 °C. This scalable platform provides a practical pathway for constructing vertically integrated complementary logic with intrinsic interconnects, paving the way for next-generation 3D system-on-chip technologies.</p>

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Reversibly Stacked Monolithic 3D Integrated Circuits

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年7月9日

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  • Tzu-Ting Weng,
  • Sung-Tsun Wang,
  • Yu-Cheng Chang,
  • Kai-Wei Li,
  • Chia-Chen Chung,
  • Chia-Hung Lo,
  • Robert Tseng,
  • Shih-Chieh Chen,
  • Tsung-Te Chou,
  • Terry Y. T. Hung,
  • Chao-Ching Cheng,
  • Iuliana P. Radu,
  • Yu-Lun Chueh,
  • Der-Hsien Lien

摘要

Monolithic three-dimensional integration enables dense vertical stacking of devices with fine-pitch interconnects, offering a promising route toward high-density, energy-efficient logic and memory systems. However, its implementation is constrained by the thermal budget of back-end-of-line processes, which must remain below 400 °C to avoid degrading underlying circuitry. While various low-temperature semiconductors have been explored, current demonstrations remain confined to fixed stacking sequences due to high-temperature growth or transfer requirements. Here, we demonstrate a M3D complementary field-effect transistor architecture using low-temperature-deposited n-type In2O3 and p-type Te semiconductors. This platform resolves existing thermal constraints, demonstrating the design freedom to reverse n- and p-type sequences. This capability enables the integration of CMOS inverters, multilayer logic stacks, and a fully functional 3D SRAM storage cell, all fabricated below 300 °C. This scalable platform provides a practical pathway for constructing vertically integrated complementary logic with intrinsic interconnects, paving the way for next-generation 3D system-on-chip technologies.