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<p>Photonic neural network chips promise compact footprint, low latency, and high energy efficiency. Yet, their scale and computing throughput are fundamentally constrained by one-dimensional input interfaces, unavoidable waveguide crossings, and the resulting crosstalk and excess loss. As a result, two-dimensional (2D) image data must be serialized through limited input ports, sacrificing spatial parallelism and creating input/output (I/O) bottlenecks. Here we demonstrate a programmable three-dimensional (3D) photonic neural network chip, fabricated by femtosecond laser direct writing (FLDW) in glass, that directly processes 2D images. The cascaded architecture alternates photonic-lantern waveguide arrays and phase-shifter arrays to implement matrix operations. An 8-layer 8 × 8 device achieves a computing throughput of 6554 TOPS, surpasses leading planar photonic platforms, and delivers 93% accuracy on MNIST classification and 94% fidelity in optical pattern generation. By combining 3D spatial parallelism with programmability, this work establishes a scalable paradigm for reconfigurable photonic computing in complex inference tasks.</p>

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Programmable Three-dimensional Photonic Neural Network Chip

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年4月21日

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  • Ziyu Cao,
  • Hong-Jing Du,
  • Xi-Jun Yuan,
  • Bo Wu,
  • Jialong Zhang,
  • Yu-Xuan Fu,
  • Shiji Zhang,
  • Wenkai Zhang,
  • Hailong Zhou,
  • Xian-Min Jin,
  • Xiao-Yun Xu,
  • Hao Tang,
  • Jianji Dong,
  • Xinliang Zhang

摘要

Photonic neural network chips promise compact footprint, low latency, and high energy efficiency. Yet, their scale and computing throughput are fundamentally constrained by one-dimensional input interfaces, unavoidable waveguide crossings, and the resulting crosstalk and excess loss. As a result, two-dimensional (2D) image data must be serialized through limited input ports, sacrificing spatial parallelism and creating input/output (I/O) bottlenecks. Here we demonstrate a programmable three-dimensional (3D) photonic neural network chip, fabricated by femtosecond laser direct writing (FLDW) in glass, that directly processes 2D images. The cascaded architecture alternates photonic-lantern waveguide arrays and phase-shifter arrays to implement matrix operations. An 8-layer 8 × 8 device achieves a computing throughput of 6554 TOPS, surpasses leading planar photonic platforms, and delivers 93% accuracy on MNIST classification and 94% fidelity in optical pattern generation. By combining 3D spatial parallelism with programmability, this work establishes a scalable paradigm for reconfigurable photonic computing in complex inference tasks.