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<p>With planar complementary metal-oxide-semiconductor (CMOS) scaling nearing its physical limits, the transistor roadmap is transitioning toward monolithic three-dimensional (M3D) integration through complementary field-effect transistors (CFETs). While silicon (Si)-CFETs demonstrate the viability of monolithic stacking, their scalability is constrained by high thermal budgets, dopant diffusion, and alignment complexity. Two-dimensional (2D) materials offer atomically thin semiconducting channels with strong electrostatics and low-temperature process compatibility, making them promising candidates for back-end-of-line (BEOL) compatible CFETs integration and potential future front-end-of-line (FEOL) replacement. This Perspective outlines the challenges and prospects for 2D CFETs, addressing 2D material synthesis, n-/p-type 2D channel engineering, low-resistance metal contact, reliable gate dielectric integration, FEOL/BEOL compatibility and interconnect co-design for M3D architectures. Furthermore, we compare the heat dissipation and energy consumption between Si-CFET and 2D-CFET with different stacking configurations, predicting the superior thermal and power-efficiency benefits of 2D channels. These insights position 2D CFETs as an attractive platform, offering a scalable and thermally efficient pathway toward the Ångström-era logic architecture.</p>

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Challenges and prospects of 2D electronics for future monolithic complementary field-effect transistors

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年4月18日

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  • Md Mobaidul Islam,
  • Yongin Cho,
  • Anamika Sen,
  • Prashant Bisht,
  • Junoh Shim,
  • Joo-On Oh,
  • Geonyong Park,
  • Antonio Rossi,
  • Hyeongwu Lee,
  • Lin Jiang,
  • Camilla Coletti,
  • Bo-In Park,
  • Heeyeop Chae,
  • SangHoon Shin,
  • Heekyeong Park,
  • Sunkook Kim

摘要

With planar complementary metal-oxide-semiconductor (CMOS) scaling nearing its physical limits, the transistor roadmap is transitioning toward monolithic three-dimensional (M3D) integration through complementary field-effect transistors (CFETs). While silicon (Si)-CFETs demonstrate the viability of monolithic stacking, their scalability is constrained by high thermal budgets, dopant diffusion, and alignment complexity. Two-dimensional (2D) materials offer atomically thin semiconducting channels with strong electrostatics and low-temperature process compatibility, making them promising candidates for back-end-of-line (BEOL) compatible CFETs integration and potential future front-end-of-line (FEOL) replacement. This Perspective outlines the challenges and prospects for 2D CFETs, addressing 2D material synthesis, n-/p-type 2D channel engineering, low-resistance metal contact, reliable gate dielectric integration, FEOL/BEOL compatibility and interconnect co-design for M3D architectures. Furthermore, we compare the heat dissipation and energy consumption between Si-CFET and 2D-CFET with different stacking configurations, predicting the superior thermal and power-efficiency benefits of 2D channels. These insights position 2D CFETs as an attractive platform, offering a scalable and thermally efficient pathway toward the Ångström-era logic architecture.