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<p>We introduce a decoding framework for correlated errors in quantum LDPC codes under circuit-level noise. Our approach is a graph augmentation and rewiring for inference (GARI) method, which modifies the correlated detector error model by eliminating 4-cycles involving <i>Y</i>-type errors, while preserving the equivalence of the decoding problem. A normalized min-sum decoder with a hybrid serial-layered schedule is applied on the transformed graph, achieving high accuracy with low latency. Performance is further enhanced (on par with XYZ-Relay-BP) through ensemble decoding, where 24 randomized normalized min-sum decoders run in parallel on the transformed graph. For the distance 12 Bivariate Bicycle code the logical error rate of (6.70&#xa0;±&#xa0;1.93)&#xa0;×&#xa0;10<sup>−9</sup> is achieved at a physical error rate of 10<sup>−3</sup>. Furthermore, preliminary FPGA implementation results show that such high accuracy can be achieved in real time, with a per-round average decoding latency of 273 ns and sub-microsecond latency in 99.99% of the decoding instances.</p>

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Decoding correlated errors in quantum LDPC codes

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年3月14日

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  • Arshpreet Singh Maan,
  • Francisco Miguel Garcia Herrero,
  • Alexandru Paler,
  • Valentin Savin

摘要

We introduce a decoding framework for correlated errors in quantum LDPC codes under circuit-level noise. Our approach is a graph augmentation and rewiring for inference (GARI) method, which modifies the correlated detector error model by eliminating 4-cycles involving Y-type errors, while preserving the equivalence of the decoding problem. A normalized min-sum decoder with a hybrid serial-layered schedule is applied on the transformed graph, achieving high accuracy with low latency. Performance is further enhanced (on par with XYZ-Relay-BP) through ensemble decoding, where 24 randomized normalized min-sum decoders run in parallel on the transformed graph. For the distance 12 Bivariate Bicycle code the logical error rate of (6.70 ± 1.93) × 10−9 is achieved at a physical error rate of 10−3. Furthermore, preliminary FPGA implementation results show that such high accuracy can be achieved in real time, with a per-round average decoding latency of 273 ns and sub-microsecond latency in 99.99% of the decoding instances.