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<p>The human brain recalls complete patterns from partial cues via associative memory, but Hopfield neural networks emulating this process are inefficient on conventional hardware, and prior memristor-based implementations are vulnerable to device defects and have limited capacity, particularly for continuous patterns. We introduce a hardware-adaptive learning algorithm that incorporates experimentally calibrated device constraints during training and validate it on an integrated memristor crossbar compute-in-memory platform. The approach improves defect tolerance and effective capacity, achieving threefold higher capacity than a pseudo-inverse baseline at 50% stuck-at faults. The same framework extends to scalable multilayer architectures supporting binary and continuous-valued patterns, where we observe superlinear capacity scaling on correlated data (∝<i>N</i><sup>1.49</sup> and ∝<i>N</i><sup>1.74</sup>, respectively). Leveraging crossbar parallelism with synchronous updates, the implementation reduces energy by 8.8× and latency by 99.7% for 64-dimensional patterns versus asynchronous schemes. These results provide a practical algorithm-hardware co-design for robust, efficient Hopfield-style associative recall.</p>

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A hardware-adaptive learning algorithm for superlinear-capacity associative memory on memristor crossbars

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年2月23日

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  • Chengping He,
  • Mingrui Jiang,
  • Keyi Shan,
  • Szu-Hao Yang,
  • Zefan Li,
  • Shengbo Wang,
  • Giacomo Pedretti,
  • Jim Ignowski,
  • Can Li

摘要

The human brain recalls complete patterns from partial cues via associative memory, but Hopfield neural networks emulating this process are inefficient on conventional hardware, and prior memristor-based implementations are vulnerable to device defects and have limited capacity, particularly for continuous patterns. We introduce a hardware-adaptive learning algorithm that incorporates experimentally calibrated device constraints during training and validate it on an integrated memristor crossbar compute-in-memory platform. The approach improves defect tolerance and effective capacity, achieving threefold higher capacity than a pseudo-inverse baseline at 50% stuck-at faults. The same framework extends to scalable multilayer architectures supporting binary and continuous-valued patterns, where we observe superlinear capacity scaling on correlated data (∝N1.49 and ∝N1.74, respectively). Leveraging crossbar parallelism with synchronous updates, the implementation reduces energy by 8.8× and latency by 99.7% for 64-dimensional patterns versus asynchronous schemes. These results provide a practical algorithm-hardware co-design for robust, efficient Hopfield-style associative recall.