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<p>Modular exponentiation is a cornerstone of public-key cryptography, yet its implementation on resource-constrained field-programmable gate arrays (FPGAs) is challenging due to limited logic elements, scarce or absent digital signal processing (DSP) blocks, and stringent power constraints. This paper presents a novel hardware architecture for modular exponentiation specifically designed to be area-efficient, low-power, and entirely DSP-free, targeting these low-end platforms. By eliminating multiplication and division operations and relying solely on addition, bit-shifting, and basic logic, the proposed algorithm significantly reduces hardware resource requirements. Experimental results on a Xilinx Artix-7 FPGA validate the approach, demonstrating minimal look-up table (LUT) and flip-flop (FF) usage, zero DSP blocks, zero block RAMs (BRAMs), and low power consumption. While this methodology results in lower computational speed compared to conventional multiplication-based solutions that heavily utilize DSP resources, this represents a deliberate trade-off to achieve significant gains in hardware efficiency and energy savings. The architecture’s compact footprint, low power profile, and predictable resource scaling make it an effective solution for integrating critical cryptographic functions into cost-sensitive, power-constrained applications, such as internet of things (IoT) devices, secure sensor nodes, and embedded systems, where resource constraints preclude high-performance implementations and moderate throughput suffices.</p>

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An area-efficient DSP-free modular exponentiation architecture for resource-constrained FPGAs

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年9月26日

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  • W. A. Susantha Wijesinghe

摘要

Modular exponentiation is a cornerstone of public-key cryptography, yet its implementation on resource-constrained field-programmable gate arrays (FPGAs) is challenging due to limited logic elements, scarce or absent digital signal processing (DSP) blocks, and stringent power constraints. This paper presents a novel hardware architecture for modular exponentiation specifically designed to be area-efficient, low-power, and entirely DSP-free, targeting these low-end platforms. By eliminating multiplication and division operations and relying solely on addition, bit-shifting, and basic logic, the proposed algorithm significantly reduces hardware resource requirements. Experimental results on a Xilinx Artix-7 FPGA validate the approach, demonstrating minimal look-up table (LUT) and flip-flop (FF) usage, zero DSP blocks, zero block RAMs (BRAMs), and low power consumption. While this methodology results in lower computational speed compared to conventional multiplication-based solutions that heavily utilize DSP resources, this represents a deliberate trade-off to achieve significant gains in hardware efficiency and energy savings. The architecture’s compact footprint, low power profile, and predictable resource scaling make it an effective solution for integrating critical cryptographic functions into cost-sensitive, power-constrained applications, such as internet of things (IoT) devices, secure sensor nodes, and embedded systems, where resource constraints preclude high-performance implementations and moderate throughput suffices.