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<p>For terahertz (THz) applications, this paper presents a novel approach to temperature regulation in Dual-Channel Double-Gate High Electron Mobility Transistors (DCDG-HEMTs). The continuous scaling of high-frequency semiconductor devices introduces significant self-heating effects that can reduce performance and reliability. To tackle this challenge, we investigate how an optimal drain-side recess length (Lrd) affects heat dissipation, electrostatic control, and RF performance. The proposed device uses a dual-channel structure based on In0.7Ga0.3As/InAs to enable enhanced carrier mobility and improved heat dissipation routes. By combining a robust Schottky barrier with a buried metal gate, localized heating is prevented and thermal resistance is further reduced. Numerical simulations using the Sentaurus TCAD tool demonstrate significant improvements in important performance metrics, including a peak transconductance of 4.77 mS/μm, a maximum drain current of 2.203&#xa0;mA/μm, and high-frequency capabilities with fT of 810&#xa0;GHz and fmax of 900&#xa0;GHz. Our findings indicate that Lrd's precision engineering maintains electrical performance while enhancing heat distribution and lowering thermal deterioration. The results validate the viability of the proposed DCDG-HEMT structure for next-generation THz applications, where efficient heat management and fast operation are essential.</p>

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Real-time AI-based thermal optimization of dual-channel double-gate HEMT for THz applications

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年7月24日

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  • R. R. Jegan,
  • R. Poornachandran,
  • G. Saravanan,
  • A. Bevin Iseac,
  • S. Mothish,
  • A. Balamurugan,
  • R. Kalaikovan

摘要

For terahertz (THz) applications, this paper presents a novel approach to temperature regulation in Dual-Channel Double-Gate High Electron Mobility Transistors (DCDG-HEMTs). The continuous scaling of high-frequency semiconductor devices introduces significant self-heating effects that can reduce performance and reliability. To tackle this challenge, we investigate how an optimal drain-side recess length (Lrd) affects heat dissipation, electrostatic control, and RF performance. The proposed device uses a dual-channel structure based on In0.7Ga0.3As/InAs to enable enhanced carrier mobility and improved heat dissipation routes. By combining a robust Schottky barrier with a buried metal gate, localized heating is prevented and thermal resistance is further reduced. Numerical simulations using the Sentaurus TCAD tool demonstrate significant improvements in important performance metrics, including a peak transconductance of 4.77 mS/μm, a maximum drain current of 2.203 mA/μm, and high-frequency capabilities with fT of 810 GHz and fmax of 900 GHz. Our findings indicate that Lrd's precision engineering maintains electrical performance while enhancing heat distribution and lowering thermal deterioration. The results validate the viability of the proposed DCDG-HEMT structure for next-generation THz applications, where efficient heat management and fast operation are essential.