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<p>In this article, we report the investigation into the stability of p-GaN gate high electron mobility transistors (HEMTs) with an internal integrated gate circuit that led to the design of a capacitance-based circuit to address threshold voltage shifts (Δ<i>V</i><sub>TH</sub>). Pulse <i>I–V</i> measurement revealed a notable positive gate <i>V</i><sub>TH</sub> shift of 0.7&#xa0;V as the drain voltage increased from 0 to 650&#xa0;V, highlighting the impact of drain bias on <i>V</i><sub>TH</sub> instability. Through the investigation of drain bias-induced <i>V</i><sub>TH</sub> instability and the behavior of carriers being transported within the gate region, it was found that the maximum Δ<i>V</i><sub>TH</sub> is 0.4&#xa0;V when a 200-V drain bias is applied; after stress removal, Δ<i>V</i><sub>TH</sub> diminishes gradually due to the discharge of capacitance, and holes enter the p-GaN layer to mitigate the depletion of holes. The integration of passive components and p-GaN gate HEMT circuits is suggested to address <i>V</i><sub>TH</sub> instability in enhancement-mode HEMT devices. The reliability of power devices is essential for their acceptance in emerging applications.</p>

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Stability of p-GaN gate AlGaN/GaN HEMTs under static and dynamic drain stress

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年6月24日

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  • Linfei Gao,
  • Xiaohua Li,
  • Wei He,
  • Xinbo Xiong,
  • Huaibao Yan,
  • Hsien-Chin Chiu,
  • Zhanwu Yang,
  • Lixuan Chen,
  • Qiubao Lin,
  • Kaifeng Wang,
  • Hezhou Liu,
  • Xinke Liu

摘要

In this article, we report the investigation into the stability of p-GaN gate high electron mobility transistors (HEMTs) with an internal integrated gate circuit that led to the design of a capacitance-based circuit to address threshold voltage shifts (ΔVTH). Pulse I–V measurement revealed a notable positive gate VTH shift of 0.7 V as the drain voltage increased from 0 to 650 V, highlighting the impact of drain bias on VTH instability. Through the investigation of drain bias-induced VTH instability and the behavior of carriers being transported within the gate region, it was found that the maximum ΔVTH is 0.4 V when a 200-V drain bias is applied; after stress removal, ΔVTH diminishes gradually due to the discharge of capacitance, and holes enter the p-GaN layer to mitigate the depletion of holes. The integration of passive components and p-GaN gate HEMT circuits is suggested to address VTH instability in enhancement-mode HEMT devices. The reliability of power devices is essential for their acceptance in emerging applications.