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<p>The increasing deployment of Internet of Things (IoT) devices has created a demand for energy-efficient and high-performance integrated circuit (IC) designs capable of continuous operation under constrained power budgets. This study introduces an efficient low-power VLSI (Lp-VLSI) design architecture specifically designed for next-generation IoT devices, incorporating sophisticated power management strategies including clock gating, power gating, multi-voltage domains, and register retention. The main objective is to reduce both dynamic and static power loss while keeping high reliability and performance. Adaptive clock gating (CG) is utilized for controlling switching activity in an approach that reduces dynamic power, while optimal power gating (PG) methods and voltage scaling are used to reduce static leakage. Multi-voltage domain partitioning allows it to move power around between functional modules, which makes the system even more energy efficient. The proposed architecture was implemented and experimentally validated on an FPGA platform under representative IoT workloads. Results from the experiments show that the proposed Lp-VLSI architecture consumes up to 23% less total power than the existing HPOA, HPVA, and LPTA architectures, 33% less dynamic power, 38% less static leakage power, 28% lower wake-up latency, 30% lower energy per operation, 21% lower thermal density, and 8% higher throughput for energy-constrained IoT applications. The platform further makes it possible for a wide range of IoT applications, from smart sensing to industrial automation, to grow. Overall, this study presents a useful way to make high-performance, low-power VLSI circuits compatible with the changing needs of smart and energy-limited IoT ecosystems.</p>

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Optimized Low-power VLSI Design for High-performance IoT Devices Using Advanced Power Management Techniques

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年8月5日

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  • L. Anbazhagan,
  • S. Senthilkumar

摘要

The increasing deployment of Internet of Things (IoT) devices has created a demand for energy-efficient and high-performance integrated circuit (IC) designs capable of continuous operation under constrained power budgets. This study introduces an efficient low-power VLSI (Lp-VLSI) design architecture specifically designed for next-generation IoT devices, incorporating sophisticated power management strategies including clock gating, power gating, multi-voltage domains, and register retention. The main objective is to reduce both dynamic and static power loss while keeping high reliability and performance. Adaptive clock gating (CG) is utilized for controlling switching activity in an approach that reduces dynamic power, while optimal power gating (PG) methods and voltage scaling are used to reduce static leakage. Multi-voltage domain partitioning allows it to move power around between functional modules, which makes the system even more energy efficient. The proposed architecture was implemented and experimentally validated on an FPGA platform under representative IoT workloads. Results from the experiments show that the proposed Lp-VLSI architecture consumes up to 23% less total power than the existing HPOA, HPVA, and LPTA architectures, 33% less dynamic power, 38% less static leakage power, 28% lower wake-up latency, 30% lower energy per operation, 21% lower thermal density, and 8% higher throughput for energy-constrained IoT applications. The platform further makes it possible for a wide range of IoT applications, from smart sensing to industrial automation, to grow. Overall, this study presents a useful way to make high-performance, low-power VLSI circuits compatible with the changing needs of smart and energy-limited IoT ecosystems.