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<p>Due to the rapid advancements in semiconductor production, increasing design complexity, and the need for gigahertz operating frequencies, designing VLSI circuits digitally presents several obstacles. Keeping power dissipation within reasonable bounds is one of the main issues designers face. The necessity for portable electronics, the shrinking transistor sizes, and the growing number of devices per chip all contribute to rising power consumption. The design and verification of very large-scale integration (VLSI) circuits depend heavily on this issue. Therefore, minimizing power dissipation throughout the design phase is crucial and requires precise power dissipation estimation. This enables the prevention of expensive and highly complex redesigns that might emerge due to violation of the power constraint. This paper presents a power estimation technique based on the backpropagation neural networks for estimating power consumption of the combinational and sequential circuits. In the proposed method, mean square error and regression analysis are used for measuring the deviations between the actual power and estimated power obtained by SPICE/Monte Carlo simulation. The deviations from the ideal power estimator using BPNN are found to be approximately 0.77% for NAND-based and 1.04% for NOR-based combinational circuits, and around 0.01% for sequential circuits. The MSE for NAND and NOR combinational circuits is 0.88751 and 1.08402, respectively, while for sequential circuits, it is approximately 6.254 × 10<sup>−5</sup>. These results demonstrate that the BPNN-based method provides highly accurate power estimation.</p>

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Intelligent Power Estimation of Digital Circuits Using Random Forest and Neural Network Models

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年10月20日

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  • R. Gowrishankar,
  • V. Govindaraj,
  • S. Sharmila Devi,
  • C. Ramesh

摘要

Due to the rapid advancements in semiconductor production, increasing design complexity, and the need for gigahertz operating frequencies, designing VLSI circuits digitally presents several obstacles. Keeping power dissipation within reasonable bounds is one of the main issues designers face. The necessity for portable electronics, the shrinking transistor sizes, and the growing number of devices per chip all contribute to rising power consumption. The design and verification of very large-scale integration (VLSI) circuits depend heavily on this issue. Therefore, minimizing power dissipation throughout the design phase is crucial and requires precise power dissipation estimation. This enables the prevention of expensive and highly complex redesigns that might emerge due to violation of the power constraint. This paper presents a power estimation technique based on the backpropagation neural networks for estimating power consumption of the combinational and sequential circuits. In the proposed method, mean square error and regression analysis are used for measuring the deviations between the actual power and estimated power obtained by SPICE/Monte Carlo simulation. The deviations from the ideal power estimator using BPNN are found to be approximately 0.77% for NAND-based and 1.04% for NOR-based combinational circuits, and around 0.01% for sequential circuits. The MSE for NAND and NOR combinational circuits is 0.88751 and 1.08402, respectively, while for sequential circuits, it is approximately 6.254 × 10−5. These results demonstrate that the BPNN-based method provides highly accurate power estimation.