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<p>Deep reinforcement learning-based methods for PCB schematic reverse generation have demonstrated substantial potential, successfully producing schematics that rival the designs of human experts in prior research. However, current methods face challenges due to limitations in exploration space stemming from a fixed layout order, as well as inefficiencies inherent in the deep reinforcement learning process. To address these challenges, for the first time, this paper proposes an component placement order prediction method based on graph neural networks, aimed at overcoming the constraints imposed by a fixed layout order. Furthermore, an invalid action masking mechanism is incorporated into the output stage of the model to reduce the invalid exploration of reinforcement learning and improve the learning efficiency. Experimental results indicate that the proposed method improves the average performance of generated schematics by approximately 11%, while also accelerating training convergence speed by around 27%. These findings validate the effectiveness and practicality of the proposed approach, offering a novel perspective and solution towards the automated design of PCB schematics.</p>

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An efficient and high-quality circuit schematic generation method based on action mask and graph neural network

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年1月5日

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  • Jie Yang,
  • Kai Qiao,
  • Jian Chen,
  • Shuhao Shi,
  • Chen Chen,
  • Bin Yan

摘要

Deep reinforcement learning-based methods for PCB schematic reverse generation have demonstrated substantial potential, successfully producing schematics that rival the designs of human experts in prior research. However, current methods face challenges due to limitations in exploration space stemming from a fixed layout order, as well as inefficiencies inherent in the deep reinforcement learning process. To address these challenges, for the first time, this paper proposes an component placement order prediction method based on graph neural networks, aimed at overcoming the constraints imposed by a fixed layout order. Furthermore, an invalid action masking mechanism is incorporated into the output stage of the model to reduce the invalid exploration of reinforcement learning and improve the learning efficiency. Experimental results indicate that the proposed method improves the average performance of generated schematics by approximately 11%, while also accelerating training convergence speed by around 27%. These findings validate the effectiveness and practicality of the proposed approach, offering a novel perspective and solution towards the automated design of PCB schematics.