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<p>The Error Detection and Correction Codes (EDCC) find applications in diverse fields where reliable communication is critical, including wireless communication systems, satellite communication, optical communication networks, and storage systems. With the exponential growth of data transmission rates and the increasing demand for robust EDCC techniques, the need for efficient codes capable of correcting multiple types of errors is becoming paramount. Conventional EDCC, such as Reed-Solomon (RS) and Hamming codes, often struggle to handle multiple adjacent and non-adjacent bit errors efficiently. While Low-Density Parity-Check (LDPC) codes have shown remarkable performance in correcting random errors, their effectiveness diminishes when facing burst errors or non-adjacent errors. Existing hybrid approaches combining LDPC with other coding techniques have been proposed; however, they often suffer from complexity issues and suboptimal performance in practical scenarios. Therefore, there remains a significant gap in EDCC techniques capable of effectively handling both adjacent and non-adjacent errors while maintaining low complexity. So, this work presents a novel design of a Hybrid Turbo LDPC (HT-LDPC) code utilizing Majority Logic Gates (MLGs) for efficient correction of multiple adjacent and non-adjacent bit errors. The proposed HT-LDPC method aims to address the challenges of error correction in various communication systems, offering significant improvements in performance and versatility. The proposed HT-LDPC scheme leverages the inherent advantages of MLGs to address the limitations of existing EDCC methods. MLGs, known for their simplicity and effectiveness in processing multiple bits simultaneously, are integrated into the LDPC coding process to enhance its error correction capabilities. By incorporating MLGs, the HT-LDPC code achieves improved performance in correcting both adjacent and non-adjacent bit errors while minimizing computational complexity. The hybrid nature of the proposed HT-LDPC method combines the strengths of LDPC and MLGs, resulting in a robust and efficient EDCC scheme suitable for various communication environments.</p>

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Design of majority logic gates-based HT-LDPC for multiple adjacent and non-adjacent bits error correction

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年11月11日

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  • Y. Vishwa Sri,
  • T. Bernatin

摘要

The Error Detection and Correction Codes (EDCC) find applications in diverse fields where reliable communication is critical, including wireless communication systems, satellite communication, optical communication networks, and storage systems. With the exponential growth of data transmission rates and the increasing demand for robust EDCC techniques, the need for efficient codes capable of correcting multiple types of errors is becoming paramount. Conventional EDCC, such as Reed-Solomon (RS) and Hamming codes, often struggle to handle multiple adjacent and non-adjacent bit errors efficiently. While Low-Density Parity-Check (LDPC) codes have shown remarkable performance in correcting random errors, their effectiveness diminishes when facing burst errors or non-adjacent errors. Existing hybrid approaches combining LDPC with other coding techniques have been proposed; however, they often suffer from complexity issues and suboptimal performance in practical scenarios. Therefore, there remains a significant gap in EDCC techniques capable of effectively handling both adjacent and non-adjacent errors while maintaining low complexity. So, this work presents a novel design of a Hybrid Turbo LDPC (HT-LDPC) code utilizing Majority Logic Gates (MLGs) for efficient correction of multiple adjacent and non-adjacent bit errors. The proposed HT-LDPC method aims to address the challenges of error correction in various communication systems, offering significant improvements in performance and versatility. The proposed HT-LDPC scheme leverages the inherent advantages of MLGs to address the limitations of existing EDCC methods. MLGs, known for their simplicity and effectiveness in processing multiple bits simultaneously, are integrated into the LDPC coding process to enhance its error correction capabilities. By incorporating MLGs, the HT-LDPC code achieves improved performance in correcting both adjacent and non-adjacent bit errors while minimizing computational complexity. The hybrid nature of the proposed HT-LDPC method combines the strengths of LDPC and MLGs, resulting in a robust and efficient EDCC scheme suitable for various communication environments.