Phase-locked loop optimization for output impedance shaping of current-source inverters with grid-side inductor voltage feedback active dampening
摘要
In comparison with the voltage source inverter (VSI), the current source inverter (CSI) does not require a feedforward point of common coupling (PCC) voltage, which eliminates the introduction of positive grid impedance voltage in the control loop. The CSI typically employs a CL filter, which can result in system resonance. To mitigate this, an active damping (AD) method is frequently employed to suppress the resonance caused by the filter. Among the AD methods, one notable approach is capacitor voltage feedback-AD (CVF-AD), and it has the advantage of simple realization. However, the amplitude of the filter capacitor voltage is usually much larger than the amplitude of the current on the DC side. This results in the system not being able to obtain the optimal damping ratio when using CVF-AD, which affects the dynamic characteristics and stability of the system. To address this challenge, this paper proposes a novel grid-side inductive voltage feedback-AD (IVF-AD) approach. This approach utilizes a block diagram equivalent transformation to enhance the robustness and stability of the system. Additionally, it considers the impact of the phase-locked loop (PLL) on system robustness when the grid impedance increases. When the grid impedance is substantial, the low harmonic amplification or instability of the inverter is more pronounced in CSI systems utilizing the time-delay-based PLL. The frequency of the instability is close to the PLL bandwidth, resulting in the existence of an active region in the phase of the output impedance. The amplitude-frequency curves of the output impedance and grid impedance are presented.