Mechanism analysis and phase-compensation suppression of zero-sequence current in dual-mode reluctance motors
摘要
To address the high noise and limited high-speed performance of conventional switched reluctance motors (SRMs), this paper proposes a switched-synchronous dual-mode reluctance motor (SSDRM). The proposed motor, through an innovative redesign of its control system architecture, integrates two excitation schemes: unipolar rectangular wave excitation and bipolar sinusoidal wave excitation. This dual-mode excitation strategy allows the motor to fully retain the advantages of SRM while reducing operational noise and increasing the speed range. While this design offers significant benefits, the dual-inverter configuration introduces a zero-sequence current (ZSC) path. Thus, suppressing the zero-sequence current becomes a critical issue for the proposed motor. This challenge distinguishes it from conventional SRMs and must be resolved. To suppress the ZSC, its generation mechanism is analyzed. An analytical model based on the Fourier series of the inductance profile is established to derive a mathematical model of the zero-sequence circuit voltage. Subsequently, by equivalently representing the SVPWM algorithm as a combination of a third harmonic and SPWM, an expression for the common-mode voltage in the dual-inverter system is derived. Based on this theoretical analysis, a phase-compensation ZSC suppression strategy is proposed for the SSDRM to achieve harmonic cancellation. The performance of the proposed motor and the effectiveness of the ZSC suppression algorithm are validated through finite element simulations and experiments.