High-reliability LDMOS with poly-Si/SiC heterojunction and buffer layer for enhanced single-event burnout tolerance
摘要
The reliability of silicon carbide lateral double-diffused metal-oxide-semiconductor (SiC LDMOS) devices in space is critically compromised by a single-event burnout (SEB), a failure mechanism primarily initiated by heavy-ion strikes. This paper presents a SEB-hardening structure that introduces a P+ poly-Si/N- SiC heterojunction and trench source design, providing a leakage path for radiation-induced carriers. This design effectively reduces the current density and avoids triggering the parasitic bipolar junction transistors (BJTs). Additionally, the incorporation of a buffer layer optimizes the electric field distribution, reduces impact ionization, and suppresses bipolar amplification, thereby preventing the self-sustaining feedback mechanism. Sentaurus TCAD simulation results demonstrate that, compared to the conventional SiC LDMOS, this hardened structure improves the SEB threshold voltage (VSEB) by over 430%, while maintaining excellent basic electrical characteristics. This paper provides a new technological approach for the design and optimization of high-reliability radiation-hardened power devices.