Hardware-Efficient Modified AES Architecture with AI-Optimized S-Box for Lightweight Applications

The raise of low-power Internet of Things (IoT) devices increases the need for lightweight cryptographic algorithms which offer adequate security while consuming fewer hardware resources. The implementation of conventional AES framework in resource constrained environment has a challenge of computational complexity. The lightweight variants such as Simplified AES (S-AES) and Modified S-AES (MS-AES) reduced the complexity but suffer from limitations such as weak S-Boxes, insufficient diffusion mechanisms, and suboptimal avalanche characteristics. At the hardware level, only limited work has integrated AI-generated components into FPGA-based lightweight cipher architectures. This work proposes a lightweight AES model that uses an AI-generated 4 × 4 S-Box with improved avalanche and balance properties, evaluated the hardware performance through FPGA implementation. Through the experimentation it is evident that the developed model shows 18% improvement in avalanche effect, 11% improvement in fitness value. The hardware implementation shows 29% reduction in LUTs, 28% reduction in both Flip-Flops and Slices. The dynamic and total power consumption of the proposed model is reduced by 30% and 28% respectively.