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<p>In this paper, efficient Authenticated encryption (AE) structures based on the LEA cipher and block cipher-based message authentication code (MAC) are proposed to provide security for IoT devices. The MAC part is designed by using block cipher-based MAC (BCMAC). In this method, the block cipher is shared between both the encryption and the MAC generation parts. Therefore, the AE structures are implemented based on low-cost circuits. The computations of the key scheduling and round function in the LEA cipher are implemented with the minimum hardware resources. The modular adder in this cipher has a low-area and high-speed circuit based on a parallel-prefix Ladner-Fischer adder. To compare the proposed structures with other works, the parameters such as area, computation time, delay, throughput, and throughput/area in 180 nm CMOS technology are analyzed. Additionally, the FPGA implementation results are presented. Based on the hardware results, we observe improvements in terms of area, throughput, and throughput/area for the proposed AE structures.</p>

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Efficient Block Cipher-Based MAC for the Authenticated Encryption Structures Based on LEA Block Cipher for the Internet of Things

  • 期刊论文

  • 发表日期：

    2026年5月20日

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  • Bahram Rashidi,
  • Leila Golpaiegany

摘要

In this paper, efficient Authenticated encryption (AE) structures based on the LEA cipher and block cipher-based message authentication code (MAC) are proposed to provide security for IoT devices. The MAC part is designed by using block cipher-based MAC (BCMAC). In this method, the block cipher is shared between both the encryption and the MAC generation parts. Therefore, the AE structures are implemented based on low-cost circuits. The computations of the key scheduling and round function in the LEA cipher are implemented with the minimum hardware resources. The modular adder in this cipher has a low-area and high-speed circuit based on a parallel-prefix Ladner-Fischer adder. To compare the proposed structures with other works, the parameters such as area, computation time, delay, throughput, and throughput/area in 180 nm CMOS technology are analyzed. Additionally, the FPGA implementation results are presented. Based on the hardware results, we observe improvements in terms of area, throughput, and throughput/area for the proposed AE structures.