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<p>A new architecture for high-speed serial-to-serial multiplication is put forth with the goal of streamlining the multiplication procedure while enhancing efficiency and lowering power usage. The suggested approach incorporates partial product production and reduction into a single serial processing framework, in contrast to traditional approaches that divide these processes. There is no requirement for an intermediate full partial product matrix because partial products are created and simultaneously compressed across n cycles. Higher bit sampling rates and effective column-wise compression are made possible by the design’s use of asynchronous 1’s counters in lieu of conventional full adders and 5:3 counters. This method considerably lowers the complexity of the ensuing adder tree by reducing the height of the partial product matrix. The design creates a hybrid column-compressed multiplier with less silicon area than traditional CSA array multipliers by combining a modified carry-save adder (CSA) array with a serial data collection unit. The proposed multiplier is ideal for on-the-fly multiplication in high data-rate applications, especially in real-time image processing systems, due to its decreased complexity, lower power consumption, and high throughput capability.</p>

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Minimized Multiplication Complexity for Image Processing Application by Using Serial Multiplier with Massive Volume of Data

  • 期刊论文

  • 发表日期：

    2026年5月20日

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  • C. Kalamani,
  • B. Radha,
  • S. Lekashri,
  • Monica Ravishankar

摘要

A new architecture for high-speed serial-to-serial multiplication is put forth with the goal of streamlining the multiplication procedure while enhancing efficiency and lowering power usage. The suggested approach incorporates partial product production and reduction into a single serial processing framework, in contrast to traditional approaches that divide these processes. There is no requirement for an intermediate full partial product matrix because partial products are created and simultaneously compressed across n cycles. Higher bit sampling rates and effective column-wise compression are made possible by the design’s use of asynchronous 1’s counters in lieu of conventional full adders and 5:3 counters. This method considerably lowers the complexity of the ensuing adder tree by reducing the height of the partial product matrix. The design creates a hybrid column-compressed multiplier with less silicon area than traditional CSA array multipliers by combining a modified carry-save adder (CSA) array with a serial data collection unit. The proposed multiplier is ideal for on-the-fly multiplication in high data-rate applications, especially in real-time image processing systems, due to its decreased complexity, lower power consumption, and high throughput capability.