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<p>As hardware designs become increasingly complex, ensuring security and correctness throughout the Integrated Circuit (IC) design lifecycle presents significant challenges. Traditional hardware design and security verification approaches, typically based on Hardware Description Languages (HDLs) such as Verilog or VHDL, often rely on manual efforts, which are time-consuming, prone to errors, and lack generalization, especially in addressing prevalent threats like hardware Trojans, side-channel vulnerabilities, etc. Recent advancements in Large Language Models (LLMs) have shown great promise in automating and enhancing various hardware security tasks through their ability to understand natural language specifications and code generation capabilities. This work presents a comprehensive survey of the state-of-the-art applications of LLMs across six critical aspects of hardware design and security: (1) HDL code generation, where LLMs translate high-level descriptions into synthesizable code; (2) HDL verification, including assertion generation and testbench automation; (3) Commercial Off-The-Shelf (COTS) hardware verification, focusing on LLM-generated test programs for black-box validation; (4) automated bug fixing, leveraging LLMs to detect vulnerabilities and generate secure patches; (5) hardware Trojan detection, where LLMs assist in identifying and explaining malicious modifications; and (6) power side-channel analysis, targeting leakage detection and mitigation. Through detailed analysis of contemporary research and empirical comparison of techniques, this paper highlights the redefining potential of LLMs in improving automation and security assurance in hardware design, while identifying open challenges and future research directions.</p>

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Harnessing the Power of LLMs for Enhancing Hardware Security

  • 期刊论文

  • 发表日期：

    2026年2月17日

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  • Sudipta Paria,
  • Swarup Bhunia

摘要

As hardware designs become increasingly complex, ensuring security and correctness throughout the Integrated Circuit (IC) design lifecycle presents significant challenges. Traditional hardware design and security verification approaches, typically based on Hardware Description Languages (HDLs) such as Verilog or VHDL, often rely on manual efforts, which are time-consuming, prone to errors, and lack generalization, especially in addressing prevalent threats like hardware Trojans, side-channel vulnerabilities, etc. Recent advancements in Large Language Models (LLMs) have shown great promise in automating and enhancing various hardware security tasks through their ability to understand natural language specifications and code generation capabilities. This work presents a comprehensive survey of the state-of-the-art applications of LLMs across six critical aspects of hardware design and security: (1) HDL code generation, where LLMs translate high-level descriptions into synthesizable code; (2) HDL verification, including assertion generation and testbench automation; (3) Commercial Off-The-Shelf (COTS) hardware verification, focusing on LLM-generated test programs for black-box validation; (4) automated bug fixing, leveraging LLMs to detect vulnerabilities and generate secure patches; (5) hardware Trojan detection, where LLMs assist in identifying and explaining malicious modifications; and (6) power side-channel analysis, targeting leakage detection and mitigation. Through detailed analysis of contemporary research and empirical comparison of techniques, this paper highlights the redefining potential of LLMs in improving automation and security assurance in hardware design, while identifying open challenges and future research directions.