An Efficient Low-Latency and High Throughput LED Cipher Architecture for IoT Security on a Hardware Platform

The recent growth of the Internet of Things (IoT) has created many significant security consequences in the modern age of electronic gadgets. In addition to their stated extent of security, IoT gadgets typically have restricted resources, like limited storage, little processing capacity, and a limited lasting battery. In the context of the IoT, lightweight cryptographic algorithms are suggested, considering the trade-off between performance and security assurance. This manuscript presents the round-based Light Encryption Device (LED) cipher architecture with key sizes of 64, 128 and 256 bits. Combinational circuits construct the four rounds of operations, which are conducted concurrently within a single clock cycle (CC) to reduce Latency and increase Throughput. The performance findings are intended to be realized by the three Mixed Column Module (MCM) techniques for the LED cipher: architecture-based, Look-Up table (LUT)-based, and Advanced Encryption Standard (AES)-based. The AES-based MCM technique provides the best results, lowering hardware complexity. The suggested designs regarding chip area and performance metrics (Latency, Throughput, and Efficiency) on Spartan-6, Virtex-6, and Artix-7 Field Programmable Gate Arrays (FPGAs) are examined. A thorough comparison of proposed three MCM-based approaches for LED Cipher is provided, focusing on various FPGA families to ensure appropriate application implementation using FPGAs. The state-of-the-art works (LED and other lightweight block ciphers) with better improvement in performance metrics on the same FPGAs are compared with the proposed LED design.