Design and Analysis of Low Power Approximate Multiplier Using Novel Compressor

The multiplier is one of the most essential arithmetic blocks in computer architecture, as it has an impact on the system’s overall performance. Approximate computing help in improving multiplier performance with low power consumption at the expense of computing precision. In this paper, approximate novel compressors are proposed and further used for the implementation of the proposed approximate multiplier. In the multiplication, process compressors are used for the reduction of partial products with low consumption of power. In comparison to the exact multiplier, the proposed multiplier shows efficient results in terms of Look-up tables, area, memory utilization, and power consumption. The validation of the approximate multiplier is done in an error-tolerant application. In this paper, validation is done in an image processing application for image blending which results in 23.87 dB and 22.7 PSNR values for set 1 and set 2 respectively.