A Novel Newton–Raphson Modulo Generator and Its VLSI Architecture for Pseudorandom Bit Generation

The existing methods for generating random numbers may get decoded, making the produced random sequences insecure, which may compromise the security of encryptions used in various communication fields. New and robust random generator methods are essential for securing communication systems. Therefore, a novel method is proposed in this paper to generate random numbers and their bits. The modified Newton–Raphson method becomes the foundation for the proposed random number generator. As a result, the Newton–Raphson modulo generator (NRMG) is the name given to the random number generator. The generated sequence of the NRMG is exponential in nature and varying, which makes them very hard to predict. Various statistical tests are performed on the generated sequence, and results reaffirm that the sequence has high non-predictability. The VLSI architecture of the proposed method is also implemented using Hardware description languages to assess their complexity during real-time implementation. This is performed through the digital signal processing (DSP) tool of the Xilinx system generator in conjunction with MATLAB. The proposed method architecture is also implemented at different bit sizes on a SOC prototype PYNQ-Z1 board for its validation.