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<p>This paper proposes a simple PWM strategy that simultaneously achieves DC-link capacitor voltage balancing and common-mode voltage (CMV) reduction for four-level (4 L) active neutral-point-clamped (ANPC) inverters. The proposed scheme is derived from the conventional carrier-overlapped PWM (COPWM) technique by rearranging the carrier disposition in phase opposition between positive- and negative-half cycles. Under the proposed strategy, inherent DC-link capacitor self-balancing is achieved while the CMV is limited to ±3VDC/18 over the entire modulation range. The method requires only a single carrier, enabling straightforward digital implementation. A closed-loop capacitor voltage control scheme is further developed to ensure robust operation under both steady-state and transient conditions. The effectiveness of the proposed PWM method has been validated through simulations on a 4.16-kV/1-MW induction motor drive system. Compared with existing techniques, the proposed approach achieves a favorable trade-off between CMV suppression and capacitor voltage balancing while maintaining competitive harmonic performance and power loss characteristics across the full operating range. The feasibility and effectiveness of the proposed strategy has been demonstrated by experimental results obtained from a 230-V/3-kW laboratory-scale induction motor drive system.</p>

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A Novel Modulation Technique for Four-level ANPC Inverters with Reduced CMV and Self-balancing Capability

  • 期刊论文

  • 发表日期：

    2026年6月30日

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  • Dinh Du To,
  • Dong-Choon Lee

摘要

This paper proposes a simple PWM strategy that simultaneously achieves DC-link capacitor voltage balancing and common-mode voltage (CMV) reduction for four-level (4 L) active neutral-point-clamped (ANPC) inverters. The proposed scheme is derived from the conventional carrier-overlapped PWM (COPWM) technique by rearranging the carrier disposition in phase opposition between positive- and negative-half cycles. Under the proposed strategy, inherent DC-link capacitor self-balancing is achieved while the CMV is limited to ±3VDC/18 over the entire modulation range. The method requires only a single carrier, enabling straightforward digital implementation. A closed-loop capacitor voltage control scheme is further developed to ensure robust operation under both steady-state and transient conditions. The effectiveness of the proposed PWM method has been validated through simulations on a 4.16-kV/1-MW induction motor drive system. Compared with existing techniques, the proposed approach achieves a favorable trade-off between CMV suppression and capacitor voltage balancing while maintaining competitive harmonic performance and power loss characteristics across the full operating range. The feasibility and effectiveness of the proposed strategy has been demonstrated by experimental results obtained from a 230-V/3-kW laboratory-scale induction motor drive system.