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<p>Estimating the power consumption of VLSI circuits at the initial phases is crucial as it enhances the functionality and reliability of the circuit. This research proposes a machine learning (ML) model to estimate the power of Complementary metal-oxide semiconductors (CMOS) VLSI circuits designed using Bayesian additive regression trees (BART) and Stacked Autoencoder (SAE) methodologies. By hybridizing the BART and SAE algorithms, the objective is to achieve a precise estimation of power using common benchmark circuits in VLSI-CMOS architecture. The research model uses the ISCAS’89 data set that includes the benchmark circuits for power estimation. Initially, the data set is preprocessed into an appropriate format like gate level and netlist representation. The feature extraction is carried out using the SAE methodology using the preprocessed and normalized data. After extracting features, the BART model is implemented for the power estimation. The proposed BART model achieved 0.135 Error%, 0.00012 Root Mean Square Error (RMSE), and 0.999 correlation coefficient. These results are compared with the current models discussed in the literature review for validation. According to the comparison of results, it is demonstrated that the proposed BART model effectively outperformed all the compared models in terms of every key metric.</p>

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Precision Power Forecasting in CMOS VLSI Circuits with a Novel BART-SAE Hybrid Model

  • 期刊论文

  • 发表日期：

    2025年6月20日

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  • K. Periyasamy,
  • G. Y. Rajaa Vikhram

摘要

Estimating the power consumption of VLSI circuits at the initial phases is crucial as it enhances the functionality and reliability of the circuit. This research proposes a machine learning (ML) model to estimate the power of Complementary metal-oxide semiconductors (CMOS) VLSI circuits designed using Bayesian additive regression trees (BART) and Stacked Autoencoder (SAE) methodologies. By hybridizing the BART and SAE algorithms, the objective is to achieve a precise estimation of power using common benchmark circuits in VLSI-CMOS architecture. The research model uses the ISCAS’89 data set that includes the benchmark circuits for power estimation. Initially, the data set is preprocessed into an appropriate format like gate level and netlist representation. The feature extraction is carried out using the SAE methodology using the preprocessed and normalized data. After extracting features, the BART model is implemented for the power estimation. The proposed BART model achieved 0.135 Error%, 0.00012 Root Mean Square Error (RMSE), and 0.999 correlation coefficient. These results are compared with the current models discussed in the literature review for validation. According to the comparison of results, it is demonstrated that the proposed BART model effectively outperformed all the compared models in terms of every key metric.