Design of Radiation Hardened SRAM Cell using Dopingless Transistor for Space Applications

The device utilized in space application demands reliable and stable static-random-access-memory (SRAM) circuits for uninterrupted and secure operation. In this paper, we have realized radiation hardened SRAM cell using dopingless transistor (DLT) and compared its performance with junctionless transistor (JLT) SRAM cell for secure and reliable operation. For realizing DL and JLT based SRAM cell, the device–circuit co-design methodology is incorporated. To reduce the impact of single event upset (SEU), the radiation hardening by design (RHBD) approach is deployed. In this technique, the resistor–capacitor (RC) circuit or RC feedback paths are connected between the input and output of cross-coupled inverter pair of SRAM cell. Using RHBD technique, the soft error (SE) sensitivity is measured and found SRAM realized with JLT and DLT are secured from the bit flipping due to SE effect. Further, the stability and performance of SRAM cells are evaluated. It is shown that hold static noise margin (HSNM) of DLT SRAM cell is improved by 7.4% in contrast to JLT SRAM cell. While, the read and write access time of DLT SRAM cell are improved by ~ 23.6% and ~ 52.4% than JLT SRAM cell. In addition, standby leakage power of DLT SRAM cell is reduced by ~ 76% than JLT SRAM. Thus, DLT SRAM cell performs faster read and write operation and consume less power which is useful for designing high-speed energy-efficient system.