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<p>Standard convolution remains a major performance bottleneck in modern deep neural networks. Although existing optimization libraries demonstrate effectiveness, they often underutilize key architectural features of emerging accelerators like DCUs, leading to suboptimal performance. To address this limitation, we propose a holistic, architecture-aware framework that systematically co-optimizes memory hierarchy and computational pipelines. The framework dynamically adapts to convolution parameters for maximal hardware utilization, with core contributions including: an innovative memory management strategy mitigating access conflicts, an adaptive computation pipeline balancing parallelism and data reuse, and a method bypassing API limitations to leverage underlying hardware instructions. On DCU hardware, our framework achieves significant speedups over MIOpen — delivering <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(3.09\times \)</EquationSource> </InlineEquation> and <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(1.64\times \)</EquationSource> </InlineEquation> average acceleration for FP16 and FP32 precision respectively, while reducing end-to-end training time for ResNet and EfficientNet by <InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(6.7\%\)</EquationSource> </InlineEquation> and <InlineEquation ID="IEq4"> <EquationSource Format="TEX">\(12.1\%\)</EquationSource> </InlineEquation>.</p>

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Optimizing Standard Convolution for Diverse Precision on DCU

  • 期刊论文

  • 发表日期：

    2025年11月18日

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  • Haobo Hua,
  • Chuangzheng Hou,
  • Zhuxin Wen,
  • Xiangkai Zhang,
  • Xiaodong Yu,
  • Jiandong Shang,
  • Litao Zhang

摘要

Standard convolution remains a major performance bottleneck in modern deep neural networks. Although existing optimization libraries demonstrate effectiveness, they often underutilize key architectural features of emerging accelerators like DCUs, leading to suboptimal performance. To address this limitation, we propose a holistic, architecture-aware framework that systematically co-optimizes memory hierarchy and computational pipelines. The framework dynamically adapts to convolution parameters for maximal hardware utilization, with core contributions including: an innovative memory management strategy mitigating access conflicts, an adaptive computation pipeline balancing parallelism and data reuse, and a method bypassing API limitations to leverage underlying hardware instructions. On DCU hardware, our framework achieves significant speedups over MIOpen — delivering \(3.09\times \) and \(1.64\times \) average acceleration for FP16 and FP32 precision respectively, while reducing end-to-end training time for ResNet and EfficientNet by \(6.7\%\) and \(12.1\%\) .