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<p>Field Programmable Gate Arrays (FPGAs) are widely used to implement the network interface controller (NIC). To measure the network traffic moving through the NIC, sketching algorithms have emerged as an accurate and storage-efficient solution. However, current FPGA-based sketch designs fail to support diverse measurement tasks sustainably. We propose FUS based on UnivMon, a multi-level universal sketch with solid theoretical guarantees for diverse measurement tasks. FUS consists of pessimistic UnivMon architecture (PUMA) and optimistic UnivMon architecture (OUMA). PUMA utilizes a homogeneous block RAM (BRAM) design, which is easy to implement but has high BRAM use. Alternatively, OUMA utilizes a heterogeneous memory design that reduces BRAM use but encounters long and uncertain off-chip memory-access latency. We use outstanding transactions to hide the long latency. Direct data forwarding and snooping are proposed to resolve the data dependencies between outstanding transactions. Write coalescing is proposed to reduce the off-chip memory-write transactions. PUMA and OUMA can sustain the maximum packet rate under 100 Gbps. Given the same BRAM budget, OUMA can achieve higher measurement quality than PUMA and the existing multi-sketch design.</p>

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FUS: FPGA-based Universal Sketch with homogeneous and heterogeneous memory architectures

  • 期刊论文

  • 发表日期：

    2025年3月28日

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  • Yunkun Liao,
  • Jingya Wu,
  • Wenyan Lu,
  • Huawei Li,
  • Xiaowei Li,
  • Guihai Yan

摘要

Field Programmable Gate Arrays (FPGAs) are widely used to implement the network interface controller (NIC). To measure the network traffic moving through the NIC, sketching algorithms have emerged as an accurate and storage-efficient solution. However, current FPGA-based sketch designs fail to support diverse measurement tasks sustainably. We propose FUS based on UnivMon, a multi-level universal sketch with solid theoretical guarantees for diverse measurement tasks. FUS consists of pessimistic UnivMon architecture (PUMA) and optimistic UnivMon architecture (OUMA). PUMA utilizes a homogeneous block RAM (BRAM) design, which is easy to implement but has high BRAM use. Alternatively, OUMA utilizes a heterogeneous memory design that reduces BRAM use but encounters long and uncertain off-chip memory-access latency. We use outstanding transactions to hide the long latency. Direct data forwarding and snooping are proposed to resolve the data dependencies between outstanding transactions. Write coalescing is proposed to reduce the off-chip memory-write transactions. PUMA and OUMA can sustain the maximum packet rate under 100 Gbps. Given the same BRAM budget, OUMA can achieve higher measurement quality than PUMA and the existing multi-sketch design.