Navigating Scaling Methods Using High-K/2D Integration in a Transistor
摘要
The integration of high-mobility semiconductors with sub-1 nm thickness and gate dielectrics exhibiting an effective oxide thickness (EOT) below 1 nm is crucial for the continuous scaling of next-generation transistors. Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as promising channel materials, paired with high-K dielectrics to meet these requirements. However, the absence of dangling bonds on 2D surfaces presents a significant challenge for atomic layer deposition (ALD) of high-K oxide using water-based oxidant, which is a typical method to grow high-K layer. This nature in 2D material leads to nucleation issues of high-K precursors during the ALD processing and finally leads to poor film quality along with device performance degradation. In this review, we discuss various strategies to enable the uniform and high-quality ALD growth of high-K oxides on 2D material, focusing on their implementation on top-gated and dual-gated transistor structures. Along with these summarized methods, we investigate switching performance using the optimized hybrid stacks. Understanding these techniques are imperative for advancing transistor scaling strategies and unlocking the full potential of 2D semiconductor-based electronics.