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<p>Amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) have garnered significant attention as key components in next-generation flexible and transparent electronics due to their high field-effect mobility, low off-state current, and excellent uniformity over large areas. A critical enabler for their integration on thermally sensitive substrates is the adoption of low-temperature fabrication processes, typically below 400 °C. However, the long-term reliability of a-IGZO TFTs remains challenged by threshold voltage (V<sub>th</sub>) instability under prolonged electrical bias and varying environmental conditions issues that are exacerbated under reduced thermal budgets. This review provides a comprehensive analysis of the intrinsic and extrinsic factors governing Vth instability in low-temperature processed a-IGZO TFTs. Particular emphasis is placed on charge trapping at the dielectric/channel interface, defect state formation within the semiconductor and gate insulator, and stress-induced phenomena such as bias-temperature stress (BTS). Additionally, various mitigation strategies including interface passivation, dopant engineering, and optimized post-deposition annealing are critically evaluated in terms of their effectiveness in improving device stability and reliability.</p>

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Enhancing Threshold Voltage Stability in Low-Temperature Processed IGZO TFTs

  • 期刊论文

  • 发表日期：

    2025年8月2日

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  • Gahong Lee,
  • Yunhui Jang,
  • Yeojin Jeong,
  • Junsin Yi

摘要

Amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) have garnered significant attention as key components in next-generation flexible and transparent electronics due to their high field-effect mobility, low off-state current, and excellent uniformity over large areas. A critical enabler for their integration on thermally sensitive substrates is the adoption of low-temperature fabrication processes, typically below 400 °C. However, the long-term reliability of a-IGZO TFTs remains challenged by threshold voltage (Vth) instability under prolonged electrical bias and varying environmental conditions issues that are exacerbated under reduced thermal budgets. This review provides a comprehensive analysis of the intrinsic and extrinsic factors governing Vth instability in low-temperature processed a-IGZO TFTs. Particular emphasis is placed on charge trapping at the dielectric/channel interface, defect state formation within the semiconductor and gate insulator, and stress-induced phenomena such as bias-temperature stress (BTS). Additionally, various mitigation strategies including interface passivation, dopant engineering, and optimized post-deposition annealing are critically evaluated in terms of their effectiveness in improving device stability and reliability.