This work provides an extensive evaluation of the Double Material Gate Charge Plasma Tunnel Field-Effect Transistor (DMG-CP-TFET), which is a new semiconductor device aimed to break the prevailing limitations of traditional transistors for nanoscale applications. Through the incorporation of dual material gates, charge plasma effects, and a dual dielectric stack ( \(SiO_{2}\) / \(HfO_{2}\) ), the designed structure achieves better carrier transport, electrostatic control, and simplicity in fabrication through the removal of doping-related variability. The study examines the vital influence of drain thickness (1 nm, 2 nm, 4 nm, and 6 nm) on device performance optimization. The results show that thinner drains (1nm–2nm) prefer vertical transport and gate control with increased current density (600 \(A/cm^{2}\) ) and electron mobility, while thicker drains (4nm–6nm) enhance lateral conduction and current uniformity due to lower scattering. Vertical versus lateral efficiency trade-offs are compared, and suggestions for application-specific design optimization are made. The DMG-CP-TFET has better scalability, energy efficiency, and reliability and is a strong contender for next-generation high-performance and low-power electronics.
