This paper introduces a novel vertical Tunnel Field-Effect Transistor (TFET) with asymmetric drain engineering, aiming to overcome the intrinsic limitations of traditional TFETs for low-power electronics. The suggested architecture utilizes a vertically stacked nanowire structure with dual high-k gate dielectrics ( \(HfO_{2}\) ) for improved electrostatic control and incorporates a new drain thickness asymmetry that maximizes carrier transport and tunneling efficiency. By strategically adjusting the drain geometry, the device produces better electric field distribution, which allows high ON-current and off-state leakage suppression. The abrupt doping profiles are employed in the design to enable band-to-band tunneling, coupled with quantum-sensitive meshing and advanced physics models (non-local BTBT, concentration-dependent mobility, and SRH recombination) for the prediction of correct performance. Simulation results indicate significant improvements in main parameters such as sub-60 mV/decade subthreshold swing, improved Ion/Ioff ratio, and low ambipolar conduction. Asymmetric drain structure provides an additional degree of freedom in the TFET optimization that allows engineered electric field profiles enhancing the tunneling probability while maintaining efficient carrier collection. This paper presents a detailed framework for vertical TFET design, providing a feasible route to energy-efficient nanoelectronics beyond the confines of conventional MOSFETs. Scalability and performance benefits of the proposed structure make it an ideal contender for future low-power logic and IoT applications.
