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<p>This article presents three novel delay elements (DEs) as core components for digitally controlled oscillators (DCOs), designed for low power and compact area. Leveraging MOS varactors and digitally controlled switches for adaptable capacitance, these DEs enable efficient frequency modulation with precise control. A multi-gate inverter structure enhances tunability while minimizing area, supporting scalable integration in advanced digital systems. All designs are simulated using TSMC 90&#xa0;nm CMOS technology at a 1&#xa0;V supply in Cadence Virtuoso. The proposed DCOs achieve low power indices of 0.002&#xa0;µW/MHz, 0.001&#xa0;µW/MHz, and 0.0047&#xa0;µW/MHz for DCO-I, DCO-II, and DCO-III, respectively, ideal for low-power applications. With DCO-I, DCO-II, and DCO-III occupying (25 × 10) µm<sup>2</sup>, (24 × 10) µm<sup>2</sup>, and (23 × 10) µm<sup>2</sup>, respectively, these designs offer a significant area advantage. Power consumption is also minimized to 9.275&#xa0;µW, 7.336&#xa0;µW, and 21.73&#xa0;µW, with DCO-II showing the lowest power usage, underscoring the effectiveness of these DEs in creating efficient DCOs for modern applications. The proposed DCO designs are validated not only at the schematic level but also through post-layout simulations, including Design Rule Check (DRC), Layout Versus Schematic (LVS) verification, and Resistance–Capacitance (RC) parasitic extraction, ensuring design robustness and practical feasibility.</p>

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High-Performance Low-Power Digital Oscillator Using CMOS Technology

  • 期刊论文

  • 发表日期：

    2025年6月6日

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  • Pritty,
  • Uma Sharma

摘要

This article presents three novel delay elements (DEs) as core components for digitally controlled oscillators (DCOs), designed for low power and compact area. Leveraging MOS varactors and digitally controlled switches for adaptable capacitance, these DEs enable efficient frequency modulation with precise control. A multi-gate inverter structure enhances tunability while minimizing area, supporting scalable integration in advanced digital systems. All designs are simulated using TSMC 90 nm CMOS technology at a 1 V supply in Cadence Virtuoso. The proposed DCOs achieve low power indices of 0.002 µW/MHz, 0.001 µW/MHz, and 0.0047 µW/MHz for DCO-I, DCO-II, and DCO-III, respectively, ideal for low-power applications. With DCO-I, DCO-II, and DCO-III occupying (25 × 10) µm2, (24 × 10) µm2, and (23 × 10) µm2, respectively, these designs offer a significant area advantage. Power consumption is also minimized to 9.275 µW, 7.336 µW, and 21.73 µW, with DCO-II showing the lowest power usage, underscoring the effectiveness of these DEs in creating efficient DCOs for modern applications. The proposed DCO designs are validated not only at the schematic level but also through post-layout simulations, including Design Rule Check (DRC), Layout Versus Schematic (LVS) verification, and Resistance–Capacitance (RC) parasitic extraction, ensuring design robustness and practical feasibility.