<p>The most of the recent embedded systems depends on the power resources and the power efficient systems are required. To achieve the power efficient systems, the ternary logic designs and graphene nanoribbon field-effect transistors (GNRFETs) are utilized over conventional binary and Silicon FETs, respectively. The ternary complex schematics such as half adder and multiplier circuits are presented in the work. The presented ternary circuits are designed by the futuristic GNRFET technology. Because, GNRFET threshold voltages are controlled by altering graphene nanoribbon (GNR) dimer line value. The industry standard Synopsys based tool i.e., HSPICE is employed for adder and multiplier circuits. The proposed circuits are developed by using the decoders, basic gates and universal gates, respectively. Thus, the decoders, basic and universal gates are also included in this study. The output responses of proposed designs are obtained and verified their functionality according to the truth tables. In addition, performances such as delay, power and power delay product (PDP) are noticed for adder and multiplier designs. Then, the acquired performances are compared with conventional CNTFET based works to confirm efficacy of presented design method. From the analysis, it is investigated that presented designs showed the improved delay, power and PDP up to 25.29%, 26.38% and 44.99% compared to CNTFET based designs. Moreover, the transistor counts of presented circuits are reduced over the conventional designs which help to improve area of integrated circuits (ICs).</p>