Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications

In this work, we have proposed a channel engineering technique for the performance enhancement of a short channel Laterally Diffused Metal–Oxide–Semiconductor (LDMOS) transistor for integrated low voltage power and RF applications. The technique involves a modification in the fabrication process flow of a conventional (CON) LDMOS to generate a device with a high graded doped channel. This device is labeled as Channel engineered (CE) LDMOS. Both devices are virtually fabricated in a process simulator with optimized implantation parameters. The impact of laterally grading the channel doping for a power device with a channel length of 0.1 µm is investigated through DC and AC device simulations. Important DC and AC performance parameters are extracted and compared with the CON device. It is seen that the CE device shows considerable improvement in transconductance (25.5%), saturated drain current (10%), output resistance (95.5%), intrinsic gain (143%), drain induced barrier lowering (53%), specific on-resistance (14%) and current on/off ratio without degrading the breakdown voltage. Small improvement is also observed in the transition frequency of the device.