Design Implementation and RF Analysis of Vertical L-Pattern Gate TFET on SELBOX Substrate

This paper presents an L-structured gate TFET which analyses the concept of vertical tunneling by incorporating n⁺ doped pocket. To ameliorate the device characteristics a wider tunnel junction area is facilitated as the channel direction remains perpendicular to the tunnel junction. Furthermore, to extricate the cumulated holes, gap has been introduced in the buried oxide layer eliminating the impact of kink. The pocket length and gap position of the design have been optimized to enhance the I_ON/I_OFF ratio. To exaggerate the ON current, the gate is designed in L-shaped enhancing the overlapping area of the gate over the channel. 54 mV/decade minimal subthreshold swing (SS) with enhanced current ratio of the order of 3.9 × 10¹² is achieved. Moreover, various RF parameters of the proposed device have been estimated by considering different range of temperature. Temperature dependency of various RF factors such as cut-off frequency (f_T), transconductance (g_m), gate capacitance (C_GG), transconductance frequency product (TFP) and intrinsic delay has been investigated in detail. The study of RF and DC parameters proves the proposed design to be a pertinent device for low power and high performance applications.